memory_map
Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
memory_map [2024/09/22 22:53] – arisotura | memory_map [2025/05/14 15:55] (current) – arisotura | ||
---|---|---|---|
Line 4: | Line 4: | ||
^ Start ^ End ^ Desc. ^ | ^ Start ^ End ^ Desc. ^ | ||
- | | 0x00000000 | 0x3FFFFFFF | main RAM (mirrored every 4MB) | | + | | 0x00000000 | 0x3FFFFFFF | main RAM (4MB, mirrored) | |
+ | | 0x00000000 | 0x00000FFF | boot ROM overlay | | ||
+ | | 0xE0010000 | 0xE001FFFF | SDIO registers (256 bytes, mirrored) | | ||
| 0xF0000000 | ? | I/O | | | 0xF0000000 | ? | I/O | | ||
- | | 0xFFFF0000 | ? | presumably bootloader | | ||
- | It is not yet known how to access the bootloader or if it exists at FFFF0000. That region reads as zero. | + | The I/O region only properly supports 32-bit writes. 16-bit and 8-bit writes will cause the incoming data to be repeated across the entire 32-bit register, ie. a 16-bit write of 0x1234 will result in 0x12341234 being written to the entire 32-bit register. |
+ | |||
+ | The SDIO region has specific | ||
+ | |||
+ | The DRH SoC (on WiiU side) has a USB device controller at 0xE0000000. Not sure if this exists at all on the gamepad. | ||
+ | |||
+ | |||
+ | ====== Boot ROM ====== | ||
+ | |||
+ | The boot ROM is mapped at 0x00000000 | ||
+ | |||
+ | When jumping to the second stage bootloader (by resetting the CPU), the boot ROM overlay is disabled. It is not completely clear how this works, but it appears that resetting the CPU does it. | ||
+ | |||
+ | The boot ROM supports three ways of loading code: SPI (from FLASH), UART (from the UART1 serial header), and I2C. It is unclear how I2C code loading would work on the gamepad, if at all (might be intended for the WiiU-side DRH SoC). | ||
Line 17: | Line 31: | ||
^ Base ^ Desc. ^ | ^ Base ^ Desc. ^ | ||
| 0xF0000000 | General registers | | | 0xF0000000 | General registers | | ||
+ | | 0xF0000100 | Device ID (16 bytes) | | ||
| 0xF0000400 | Timers | | | 0xF0000400 | Timers | | ||
- | | 0xF0000800 | ? | | + | | 0xF0000800 |
+ | | 0xF0000C00 | ||
| 0xF0001200 | IRQ controller | | | 0xF0001200 | IRQ controller | | ||
| 0xF0001300 | IRQ controller | | | 0xF0001300 | IRQ controller | | ||
| 0xF0001400 | IRQ controller | | | 0xF0001400 | IRQ controller | | ||
| 0xF0001900 | IRQ controller | | | 0xF0001900 | IRQ controller | | ||
- | | 0xF0004000 | DMA | | + | | 0xF0004000 | DMA - general registers and peripheral DMA | |
+ | | 0xF0004100 | DMA - general purpose | ||
| 0xF0004400 | SPI | | | 0xF0004400 | SPI | | ||
+ | | 0xF0004800 | SDIO | | ||
+ | | 0xF0004C00 | UART | | ||
| 0xF0005000 | GPIO | | | 0xF0005000 | GPIO | | ||
| 0xF0005100 | GPIO | | | 0xF0005100 | GPIO | | ||
+ | | 0xF0005200 | ??? | | ||
| 0xF0005400 | Audio | | | 0xF0005400 | Audio | | ||
| 0xF0005800 | I2C general registers | | | 0xF0005800 | I2C general registers | | ||
+ | | 0xF0005900 | I2C bus 0? | | ||
| 0xF0005C00 | I2C bus 1 | | | 0xF0005C00 | I2C bus 1 | | ||
+ | | 0xF0005D00 | I2C bus 1 | | ||
| 0xF0006000 | I2C bus 2 | | | 0xF0006000 | I2C bus 2 | | ||
| 0xF0006400 | I2C bus 3 | | | 0xF0006400 | I2C bus 3 | | ||
| 0xF0006800 | I2C bus 4 | | | 0xF0006800 | I2C bus 4 | | ||
- | | 0xF0009400 | + | | 0xF0008400 |
- | | F0009500 | + | | 0xF0008800 |
- | | F0009600 | + | | 0xF0008900 |
- | | F0009700 | + | | 0xF0008C00 |
+ | | 0xF0009000 | Video - camera controller related? | | ||
+ | | 0xF0009400 | Video - output/ | ||
+ | | 0xF0009500 | Video - palette | | ||
+ | | 0xF0009600 | Video - color correction | | ||
+ | | 0xF0009700 | Video - timings? | | ||
memory_map.1727045583.txt.gz · Last modified: 2024/09/22 22:53 by arisotura