The gamepad has a pretty simple memory map.

The I/O region only properly supports 32-bit writes. 16-bit and 8-bit writes will cause the incoming data to be repeated across the entire 32-bit register, ie. a 16-bit write of 0x1234 will result in 0x12341234 being written to the entire 32-bit register.

The SDIO region has specific access requirements for each register, and trying to write to a register with the wrong size is simply ignored. TODO: document exactly which registers require which sizes.

The DRH SoC (on WiiU side) has a USB device controller at 0xE0000000. Not sure if this exists at all on the gamepad.

The boot ROM is mapped at 0x00000000 as an overlay. Writes go through to main RAM.

When jumping to the second stage bootloader (by resetting the CPU), the boot ROM overlay is disabled. It is not completely clear how this works, but it appears that resetting the CPU does it.

The boot ROM supports three ways of loading code: SPI (from FLASH), UART (from the UART1 serial header), and I2C. It is unclear how I2C code loading would work on the gamepad, if at all (might be intended for the WiiU-side DRH SoC).

The I/O region is split into basic blocks for the various hardware components.