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−Table of Contents
I2C
The I2C interface connects the LCD, audio amplifier and camera to the CPU.
There are two possible I2C controllers. If the LSB of register 0xF0000000 is 0x41, the gamepad has the Samsung controller, otherwise it has the Renesas controller.
In practice, I have only seen Renesas controllers so far, so I don't know how rare the Samsung one is.
There are 4 I2C busses, referred to as 1, 2, 3 and 4. Bus 1 appears to be for slave mode, while the others are for master mode. In practice, all the I2C devices are on bus 3, leaving the others unused.
The I2C registers are distributed as follows:
Base address | Desc. |
---|---|
0xF0005800 | General I2C registers |
0xF0005C00 | Bus 1 |
0xF0006000 | Bus 2 |
0xF0006400 | Bus 3 |
0xF0006800 | Bus 4 |
General registers
These registers control the individual busses.
Address | Desc. |
---|---|
0xF0005800 | IRQ flags |
0xF0005804 | Bus enable |
0xF0005808 | IRQ acknowledge |
In each register, bit0..3 corresponds to bus 1..4.
Renesas controller
Slave mode (bus 1)
Offset | Desc. |
---|---|
0x104 | ?? |
0x108 | ?? |
0x138 | Data 0 |
0x13C | Data 1 |
Master mode (bus 2..4)
Offset | Desc. |
---|---|
0x004 | Data input/output |
0x008 | Transfer control |
0x018 | Transfer status |
0x020 | Status register |
Base+0x004
Data input/output.
Base+0x008
Transfer control.
Bits | Desc. |
---|---|
0 | Stop |
1 | ?? |
2 | Read mode |
3 | Write mode |
4 | Start |
5 | Request data (when reading) |
Bit 0 appears to be write-only.
Bit 5 gets cleared after a data byte is received.
TODO: bit 5 is also set at the end of a read??
Base+0x018
Transfer status.
Bits | Desc. |
---|---|
0 | Stop |
1 | Start |
2 | Ack (from remote) |
3 | Direction; 0=reading, 1=writing |
7 | Transfer pending |
Samsung controller
Slave mode (bus 1)
TODO
Master mode (bus 2..4)
Offset | Desc. |
---|---|
0x000 | Transfer control?? |
0x004 | ?? |
0x00C | Data input/output |
0x010 | ?? |