WiiU Gamepad Technical Documentation

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uart [2025/04/19 17:33] – arisoturauart [2025/05/10 11:55] (current) – arisotura
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 | 0x0C   | IRQ status | | 0x0C   | IRQ status |
 | 0x10   | ?? | | 0x10   | ?? |
-| 0x14   | speed related (greater = slower) |+| 0x14   | Serial settings |
 | 0x18   | ?? | | 0x18   | ?? |
 | 0x1C   | Status register | | 0x1C   | Status register |
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 Data output. Data output.
  
-Data received can be read out from this register.+Data received can be read out from this register. If data is received while the FIFO is already full, the RX error IRQ is raised.
  
  
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 **Base+0x08** **Base+0x08**
 +
 +IRQ enable.
  
 ^ Bits ^ Desc. ^ ^ Bits ^ Desc. ^
 | 0    | Enable RX IRQ (4) | | 0    | Enable RX IRQ (4) |
 | 1    | Enable TX IRQ (2) | | 1    | Enable TX IRQ (2) |
-| 2    | Enable RX fail IRQ (6) |+| 2    | Enable RX error IRQ (6) |
  
  
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 IRQ 4 is fired when a byte of data is received. To acknowledge it, read the data from the data output port. IRQ 4 is fired when a byte of data is received. To acknowledge it, read the data from the data output port.
  
-IRQ 6 is fired when data reception fails. For example this happens if the RX line is pulled low (when polarity set to active high). The only known way to acknowledge this IRQ is to reset the UART entirely.+IRQ 6 is fired when data reception fails. For example this happens if the RX line is pulled low (when polarity set to active high). This also happens on parity errors. The only known way to acknowledge this IRQ is to reset the UART entirely. 
 + 
 +Unknown what IRQ 12 would be. Firmware code has a case for it, but I haven't observed it so far. 
 + 
 + 
 +**Base+0x14** 
 + 
 +Serial settings. 
 + 
 +^ Bits ^ Desc. ^ 
 +| 0-1  | Data bits; 0=5 bits, 1=6 bits, 2=7 bits, 3=8 bits | 
 +| 2    | Stop bits; 0=1 bit, 1=2 bits | 
 +| 3    | Enable parity bit | 
 +| 4    | Parity; 0=odd, 1=even | 
 +| 5    | ??? (no effect observed) | 
 +| 6    | ??? (causes TX line to be held low) |
  
  
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 | 0    | RX FIFO not empty | | 0    | RX FIFO not empty |
 | 1    | RX FIFO overflow (received data while FIFO already full) | | 1    | RX FIFO overflow (received data while FIFO already full) |
 +| 2    | RX parity error |
 +| 3    | RX error, ? (FIFO overflow?) |
 | 4    | RX line error (ie. line held low) | | 4    | RX line error (ie. line held low) |
 | 5    | 1 when ready to send, 0 when sending | | 5    | 1 when ready to send, 0 when sending |
Line 117: Line 136:
 ^ Bits ^ Desc. ^ ^ Bits ^ Desc. ^
 | 0    | Enable UART | | 0    | Enable UART |
-| 1    | Bit order; 0=LSb first, 1=MSb first |+| 1    | Data bit order; 0=LSb first, 1=MSb first |
 | 2    | Line polarity; 0=active high, 1=active low | | 2    | Line polarity; 0=active high, 1=active low |
  
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 ^ Bits ^ Desc. ^ ^ Bits ^ Desc. ^
-| 0-2  | RX state |+| 0-3  | RX state |
 | 8-12 | RX FIFO level (occupied space, 0..16) | | 8-12 | RX FIFO level (occupied space, 0..16) |
  
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   * 2 = receiving data bit   * 2 = receiving data bit
   * 7 = waiting for next data bit?   * 7 = waiting for next data bit?
-  * 4 = receiving stop bit+  * 3 = receiving parity bit 
 +  * 8 = checking parity bit? 
 +  * 9 = waiting for stop bits after parity bit? 
 +  * 4 = receiving stop bits
   * 10 = storing byte into FIFO   * 10 = storing byte into FIFO
   * 0 = idle   * 0 = idle
Line 146: Line 168:
  
 ^ Bits ^ Desc. ^ ^ Bits ^ Desc. ^
-| 0-2  | TX state |+| 0-3  | TX state |
 | 8-12 | TX FIFO level (occupied space, 0..16) | | 8-12 | TX FIFO level (occupied space, 0..16) |
  
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   * 1 = sending start bit   * 1 = sending start bit
   * 2 = sending data bits   * 2 = sending data bits
-  * 4 = sending stop bit+  * 3 = sending parity bit 
 +  * 4 = sending stop bits
   * 0 = idle   * 0 = idle
  
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 ^ Bits ^ Desc. ^ ^ Bits ^ Desc. ^
-| 0-4  | ??? |+| 0-3  | ??? | 
 +| 4    | Aux. LED (for UART2) (0=off, 1=on) |
 | 8-14 | ??? | | 8-14 | ??? |
  
 Default value 0x102. Default value 0x102.
  
-Bit 0 seems to break clocking/timing logic?+Bit 0 seems to break clocking/timing logic? When it is set, data is still clocked out, but in a very fast and broken way (and completely ignores all clock settings).
  
  
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 The input clock can be configured in the [[General registers|clock registers]]. Each UART gets its own clock register: 0xF0000040 for UART0, 0xF0000044 for UART1, and 0xF0000048 for UART2. The input clock can be configured in the [[General registers|clock registers]]. Each UART gets its own clock register: 0xF0000040 for UART0, 0xF0000044 for UART1, and 0xF0000048 for UART2.
 +
 +Here is a table of settings for common baud rates, given an input clock of 16 MHz:
 +
 +^ Baud rate ^ Divider 1 ^ Multiplier ^ Divider 2 ^
 +| 4800      | 1         | 3          | 625       |
 +| 9600      | 1         | 6          | 625       |
 +| 19200     | 1         | 12         | 625       |
 +| 38400     | 1         | 24         | 625       |
 +| 57600     | 1         | 36         | 625       |
 +| 115200    | 1         | 72         | 625       |
 +| 230400    | 1         | 144        | 625       |
 +| 460800    | 1         | 288        | 625       |
 +| 921600    | 1         | 576        | 625       |
  
 The diagnostics firmware contains code (at 0xAC0EE) to calculate the multiplier/divider register parameters for a given baud rate based on the current UART input clock. However, that function produces incorrect results for certain baud rates. The diagnostics firmware contains code (at 0xAC0EE) to calculate the multiplier/divider register parameters for a given baud rate based on the current UART input clock. However, that function produces incorrect results for certain baud rates.
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 Output ''mul'' and ''div'' parameters can be applied to the multiplier and divider 2 registers, respectively. Divider 1 will be set to 1. Output ''mul'' and ''div'' parameters can be applied to the multiplier and divider 2 registers, respectively. Divider 1 will be set to 1.
  
 +
 +===== Using with DMA =====
 +
 +Much like SPI, the UARTs can be used conjointly with [[DMA]] channels 0 or 1.
 +
 +To send data using DMA, you simply start a write DMA transfer instead of manually writing data to the UART's data output port. You should rely on the TX IRQ (2) to detect transfer completion.
 +
 +To receive data using DMA, you can start a read DMA transfer at any moment. The DMA transfer will complete when the requested amount of bytes has been received. Note that if a read DMA transfer is active on the UART, it will suppress the RX IRQ. Thus, you should rely on the DMA completion IRQ to detect transfer completion.
uart.1745084036.txt.gz · Last modified: 2025/04/19 17:33 by arisotura
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