Differences

This shows you the differences between two versions of the page.

--- memory_map [2025/05/08 20:12] – arisotura
+++ memory_map [2025/05/14 15:55] (current) – arisotura
@@ Line 5: / Line 5: @@
 ^ Start      ^ End        ^ Desc.          ^
 | 0x00000000 | 0x3FFFFFFF | main RAM (4MB, mirrored) |
-| 0x00000000 | 0x0000047F | boot ROM overlay |
+| 0x00000000 | 0x00000FFF | boot ROM overlay |
 | 0xE0010000 | 0xE001FFFF | SDIO registers (256 bytes, mirrored) |
 | 0xF0000000 | ?          | I/O            |
@@ Line 20: / Line 20: @@
 The boot ROM is mapped at 0x00000000 as an overlay. Writes go through to main RAM.
-Before jumping to the second stage bootloader, the boot ROM disables its overlay, presumably by setting bit 12 in register 0xF0000000.
+When jumping to the second stage bootloader (by resetting the CPU), the boot ROM overlay is disabled. It is not completely clear how this works, but it appears that resetting the CPU does it.
+The boot ROM supports three ways of loading code: SPI (from FLASH), UART (from the UART1 serial header), and I2C. It is unclear how I2C code loading would work on the gamepad, if at all (might be intended for the WiiU-side DRH SoC).
@@ Line 31: / Line 33: @@
 | 0xF0000100 | Device ID (16 bytes) |
 | 0xF0000400 | Timers |
-| 0xF0000800 | ? |
+| 0xF0000800 | Camera controller |
 | 0xF0000C00 | ? |
 | 0xF0001200 | IRQ controller |
@@ Line 53: / Line 55: @@
 | 0xF0006400 | I2C bus 3 |
 | 0xF0006800 | I2C bus 4 |
-| 0xF0008400 | Video capture?? |
+| 0xF0008400 | Video - h264 encoder? |
 | 0xF0008800 | Video capture?? |
 | 0xF0008900 | Video capture?? |
 | 0xF0008C00 | Video capture?? |
-| 0xF0009000 | Video - ? |
+| 0xF0009000 | Video - camera controller related? |
 | 0xF0009400 | Video - output/framebuffer |
 | 0xF0009500 | Video - palette |