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lcd_controller [2025/03/18 02:55] arisoturalcd_controller [2025/05/17 00:05] (current) arisotura
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 ====== LCD controller ====== ====== LCD controller ======
  
-The gamepad provides simple framebuffer-based display hardware.+The gamepad provides simple display hardware that can display a video feed (from the camera or the H264 decoder) and a framebuffer overlay on top.
  
 Register map: Register map:
Line 13: Line 13:
 | 0xF0009418 | Horizontal end of display | | 0xF0009418 | Horizontal end of display |
 | 0xF000941C | Vertical end of display | | 0xF000941C | Vertical end of display |
-| 0xF0009420 | ?? +| 0xF0009420 | Video feed X offset 
-| 0xF0009424 | ?? | +| 0xF0009424 | Video feed width | 
-0xF0009428 | ?? |+| 0xF0009428 | Video feed Y offset | 
 +| 0xF000942C | Video feed height | 
 +| 0xF0009430 | ?? | 
 +0xF0009434 | ?? |
 | 0xF0009460 | Framebuffer X offset | | 0xF0009460 | Framebuffer X offset |
 | 0xF0009464 | Framebuffer width | | 0xF0009464 | Framebuffer width |
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 | 0xF0009470 | Framebuffer stride | | 0xF0009470 | Framebuffer stride |
 | 0xF0009474 | Framebuffer address | | 0xF0009474 | Framebuffer address |
 +| 0xF0009478 | ?? |
 | 0xF0009480 | Display control | | 0xF0009480 | Display control |
 +| 0xF0009484 | ?? |
 +| 0xF0009488 | ?? |
 +| 0xF0009490 | ?? |
 +| 0xF0009494 | ?? |
 | 0xF00094B0 | Pixel format | | 0xF00094B0 | Pixel format |
 | 0xF00094B4 | ?? | | 0xF00094B4 | ?? |
 +| 0xF00094B8 | ?? |
 +| 0xF00094BC | ?? |
 +| 0xF00094C0 | ?? |
 +| 0xF00094C4 | ?? |
 +| 0xF00094C8 | VCount - current vertical position |
 +| 0xF00094D0+(N*4) | YUV->RGB matrix (N=0..8) |
 +| 0xF00094F4 | ?? |
 +| 0xF00094F8 | Camera sync |
 +| 0xF00094FC | Counter of sorts |
 +| ||
 | 0xF0009500 | Palette address | | 0xF0009500 | Palette address |
 | 0xF0009504 | Palette data | | 0xF0009504 | Palette data |
-| 0xF0009508 | ?? +| 0xF0009508 | VCount IRQ position 1 
-| 0xF000950C | ?? +| 0xF000950C | VCount IRQ position 2 
-| 0xF0009510 | ?? +| 0xF0009510 | VCount IRQ position 3 
-| 0xF0009514 | ?? +| 0xF0009514 | VCount IRQ position 4 | 
-| 0xF0009600+(N*4) | Color correction LUT entry N |+| |
 +| 0xF0009600+(N*4) | Color correction LUT entry N (N=0..31) |
 | 0xF0009684 | Color correction mask | | 0xF0009684 | Color correction mask |
 +| ||
 | 0xF0009700 | ?? | | 0xF0009700 | ?? |
 | 0xF0009704 | ?? | | 0xF0009704 | ?? |
 | 0xF0009708 | ?? | | 0xF0009708 | ?? |
 +
 +Related IRQs:
 +
 +^ IRQ  ^ Desc. ^
 +| 0x12 | ?? |
 +| 0x15 | Display start (VBlank end) |
 +| 0x16 | VBlank |
 +| 0x1E | VCount match |
  
 The LCD pixel clock is, by default, 32 MHz. It is sourced from [[General_registers|register 0xF0000034]]. The LCD pixel clock is, by default, 32 MHz. It is sourced from [[General_registers|register 0xF0000034]].
Line 127: Line 155:
 ^ Bits ^ Desc. ^ ^ Bits ^ Desc. ^
 | 0    | ?? breaks display | | 0    | ?? breaks display |
-| 1    | Must be set for display to work. Presumably enables overlay. +| 1    | Enable display (0=black screen) 
-| 2    | ?? causes weird effects +| 2    | Enable video feed (camera/H264?
-| 3    | ?? | +| 3    | Video feed input(0=post-processed camera?, 1=raw camera?
-| 4    | Must be set for display to work. Presumably general display enable. +| 4    | Enable overlay |  
 +| 5    | ?? | 
 +| 6    | ?? |
  
 **0xF00094B0** **0xF00094B0**
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 | 2    | ?? | | 2    | ?? |
 | 3    | ?? | | 3    | ?? |
 +| 7    | Color mode; 0=RGB, 1=YUV |
 +| 8    | ?? collapses overlay to 1px vertical line |
 +| 9    | ?? |
 +| 10   | ?? |
 | 16-23 | ?? (set to 0xFF) | | 16-23 | ?? (set to 0xFF) |
  
Line 150: Line 184:
  
 For the paletted formats, see the palette registers. For the paletted formats, see the palette registers.
 +
 +Bit 7 causes color components to be interpreted as YUV, with the following mapping: R=V, G=Y, B=U. It seems the handling is different based on the pixel format? Notably, in YUV mode, pixel formats 0 and 1 seem to entirely ignore the palette and instead somehow directly convert indices to color components.
 +
 +In YUV mode, the matrix at 0xF00094D0..0xF00094F0 is used to convert the YUV components to RGB.
 +
 +
 +**0xF00094C8**
 +
 +Current vertical position.
 +
 +
 +**0xF00094D0+(N*4)**
 +
 +YUV->RGB matrix.
 +
 +^ Register   ^ Description   ^ Default value |
 +| 0xF00094D0 | Y -> G factor | 0x0A5 = 74 |
 +| 0xF00094D4 | U -> G factor | 0x04E = -14 |
 +| 0xF00094D8 | V -> G factor | 0x062 = -34 |
 +| 0xF00094DC | Y -> B factor | 0x0A5 = 74 |
 +| 0xF00094E0 | U -> B factor | 0x122 = 136 |
 +| 0xF00094E4 | V -> B factor | 0x000 = 0 |
 +| 0xF00094E8 | Y -> R factor | 0x0A5 = 74 |
 +| 0xF00094EC | U -> R factor | 0x000 = 0 |
 +| 0xF00094F0 | V -> R factor | 0x0B9 = 114 |
 +
 +The factors work in a bit of a weird way.
 +
 +^ Bits ^ Desc. ^
 +| 0-5  | Amount |
 +| 6    | Sign |
 +| 7-8  | Multiplier; 0=1, 1=2, 2/3=4 |
 +
 +The sign bit makes the value negative, but it's not two's complement. Instead: 0x3F = 63, 0x7F = -63.
 +
 +The multiplier allows to increase the final value. For example, values 0x30, 0x98, 0x10C and 0x18C are equivalent.
 +
 +Note: YUV mode produces darker colors, even with maximum factor values. One can use the color correction registers at 0xF0009600 to compensate for this.
 +
 +
 +**0xF00094F8**
 +
 +Camera sync.
 +
 +^ Bits ^ Desc. ^
 +| 0-10 | Vertical position |
 +| 15   | ??? |
 +
 +This register allows to synchronize camera output to the display. The camera frame IRQ fires 8 scanlines after the specified position.
 +
 +This register can be disabled by setting it to a value equal to or greater than the display's total vertical span (as set in 0xF0009404). In this case, the camera outputs at its 'natural' framerate without synchronizing to the display, and the camera frame IRQ fires whenever a frame is finished.
 +
 +
 +**0xF00094FC**
 +
 +Counter of sorts. Seems to be based on the [[timers|count-up timer]].
 +
 +This register is 27 bits wide.
  
  
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 The color format is ARGB8888. The MSB of color values seems to actually function as an alpha value, which suggests that the LCD controller may be able to blend the framebuffer with something else, presumably output from the video decoder. The color format is ARGB8888. The MSB of color values seems to actually function as an alpha value, which suggests that the LCD controller may be able to blend the framebuffer with something else, presumably output from the video decoder.
 +
 +
 +===== VCount IRQ registers =====
 +
 +**0xF0009508 to 0xF0009514**
 +
 +These registers allow to trigger IRQ 0x1E based on the current vertical position (VCount).
 +
 +When VCount matches any of these registers, IRQ 0x1E is triggered. The multiple registers allow to split the frame time in smaller intervals.
 +
 +These registers are 11 bits wide. They can be 'disabled' by setting them to a value outside of the configured vertical range.
 +
 +The stock firmware uses IRQ 0x1E to perform input polling and audio sync. The settings it uses divide each frame into 3 equal parts, effectively firing IRQ 0x1E at a 180 Hz interval.
  
  
lcd_controller.1742266502.txt.gz · Last modified: 2025/03/18 02:55 by arisotura

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