i2c
Differences
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| i2c [2024/09/26 13:11] – arisotura | i2c [2025/04/20 11:51] (current) – arisotura | ||
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| There are two possible I2C controllers. If the LSB of [[General registers|register 0xF0000000]] is 0x41, the gamepad has the Samsung controller, otherwise it has the Renesas controller. | There are two possible I2C controllers. If the LSB of [[General registers|register 0xF0000000]] is 0x41, the gamepad has the Samsung controller, otherwise it has the Renesas controller. | ||
| - | In practice, I have only seen Renesas controllers so far, so I don't know how rare the Samsung one is. | + | In practice, I have only seen Renesas controllers so far, so I don't know how rare the Samsung one is. Considering that the I2C controller is part of the SoC, it is likely that the Samsung controller is solely prototype stuff. As further evidence, the diagnostics firmware only supports the Renesas controller. |
| - | There are 4 I2C busses, referred to as 1, 2, 3 and 4. Bus 1 appears to be for slave mode, while the others are for master mode. In practice, all the I2C devices are on bus 3, leaving the others unused. | + | There are 5 I2C busses, referred to as 0, 1, 2, 3 and 4. Busses 0 and 1 appears to be for slave mode, while the others are for master mode. In practice, all the I2C devices are on bus 3, leaving the others unused. It isn't even known if the other busses have any connections outside of the DRC SoC. Busses 2 and 4 are nonfunctional. |
| The I2C registers are distributed as follows: | The I2C registers are distributed as follows: | ||
| ^ Base address ^ Desc. ^ | ^ Base address ^ Desc. ^ | ||
| - | | 0xF0005800 | + | | 0xF0005800 |
| | 0xF0005C00 | | 0xF0005C00 | ||
| | 0xF0006000 | | 0xF0006000 | ||
| Line 24: | Line 24: | ||
| ^ Address | ^ Address | ||
| | 0xF0005800 | IRQ flags | | | 0xF0005800 | IRQ flags | | ||
| - | | 0xF0005804 | Bus enable | | + | | 0xF0005804 | IRQ enable | |
| | 0xF0005808 | IRQ acknowledge | | | 0xF0005808 | IRQ acknowledge | | ||
| - | In each register, bit0..3 corresponds to bus 1..4. | + | In each register, bit0..4 corresponds to bus 0..4. |
| ===== Renesas controller ===== | ===== Renesas controller ===== | ||
| - | ==== Slave mode (bus 1) ==== | + | ==== Slave mode (bus 0..1) ==== |
| ^ Offset ^ Desc. ^ | ^ Offset ^ Desc. ^ | ||
| Line 52: | Line 52: | ||
| - | **Base+0x004** | + | **0xF0006x04** |
| Data input/ | Data input/ | ||
| - | **Base+0x008** | + | **0xF0006x08** |
| Transfer control. | Transfer control. | ||
| Line 78: | Line 78: | ||
| - | **Base+0x018** | + | **0xF0006x18** |
| Transfer status. | Transfer status. | ||
| ^ Bits ^ Desc. ^ | ^ Bits ^ Desc. ^ | ||
| - | | 0 | Stop | | + | | 0 | Stop generated |
| - | | 1 | Start | | + | | 1 | Start generated |
| | 2 | Ack (from remote) | | | 2 | Ack (from remote) | | ||
| | 3 | Direction; 0=reading, 1=writing | | | 3 | Direction; 0=reading, 1=writing | | ||
| | 7 | Transfer pending | | | 7 | Transfer pending | | ||
| + | |||
| + | |||
| + | **0xF0006x20** | ||
| + | |||
| + | Status register of sorts. | ||
| + | |||
| + | ^ Bits ^ Desc. ^ | ||
| + | | 0 | ??? | | ||
| + | | 1 | ??? gets cleared | | ||
| + | | 6 | Transfer pending | | ||
| + | | 7 | ??? | | ||
| Line 104: | Line 115: | ||
| | 0x00C | Data input/ | | 0x00C | Data input/ | ||
| | 0x010 | ?? | | | 0x010 | ?? | | ||
| + | |||
| + | |||
| + | ===== I2C devices ===== | ||
| + | |||
| + | The following devices are connected to the I2C interface: | ||
| + | ^ Bus ^ Device ID ^ Device ^ | ||
| + | | 3 | 0x18 | [[Audio amplifier]] | | ||
| + | | 3 | 0x21 | Camera | | ||
| + | | 3 | 0x39 | [[LCD]] | | ||
i2c.1727356312.txt.gz · Last modified: 2024/09/26 13:11 by arisotura