general_registers
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| general_registers [2025/05/09 22:03] – arisotura | general_registers [2025/10/15 21:16] (current) – arisotura | ||
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| Line 140: | Line 140: | ||
| | 14 | Reset I2C4 | | | 14 | Reset I2C4 | | ||
| | 15 | Reset audio controller | | | 15 | Reset audio controller | | ||
| - | | 16 | Reset ??? (0xF0008400) | | + | | 16 | Reset H264 codec (0xF0008400) | |
| | 17 | ??? | | | 17 | ??? | | ||
| | 18 | Reset ??? (0xF0008800, | | 18 | Reset ??? (0xF0008800, | ||
| | 19 | Reset ??? (0xF0008C00) | | | 19 | Reset ??? (0xF0008C00) | | ||
| - | | 20 | Reset ??? (0xF0009000) | | + | | 20 | Reset camera controller |
| | 21 | Reset LCD controller (0xF0009400, | | 21 | Reset LCD controller (0xF0009400, | ||
| Line 259: | Line 259: | ||
| | 2 | ??? | ??? | | | 2 | ??? | ??? | | ||
| | 3 | 3.08 MHz | Audio bit clock (from [[audio amplifier]]) | | | 3 | 3.08 MHz | Audio bit clock (from [[audio amplifier]]) | | ||
| - | | 4 | 864 MHz | Primary clock | | + | | 4 | 864 MHz |
| - | | 5 | 3.38 MHz | Secondary clock 1 | | + | | 5 | 3.38 MHz | PLL - Secondary clock 1 | |
| - | | 6 | 16 MHz | Secondary clock 2 | | + | | 6 | 16 MHz | PLL - Secondary clock 2 | |
| - | | 7 | 3.38 MHz | Secondary clock 3 | | + | | 7 | 3.38 MHz | PLL - Secondary clock 3 | |
| Peripherals may then divide their incoming clocks further. For example, in the case of I2C, the clock is divided by 24 before being output to the SCL line. | Peripherals may then divide their incoming clocks further. For example, in the case of I2C, the clock is divided by 24 before being output to the SCL line. | ||
general_registers.1746828190.txt.gz · Last modified: 2025/05/09 22:03 by arisotura