WiiU Gamepad Technical Documentation

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general_registers

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general_registers [2025/05/09 14:29] – arisoturageneral_registers [2025/10/15 21:16] (current) – arisotura
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 The boot ROM checks bits 17-18 to determine where to load the second stage bootloader from. Those bits can be controlled by the [[test_points#serial_header|serial header]]: shorting pad 2 to ground sets those bits to 0, enabling UART boot. The boot ROM checks bits 17-18 to determine where to load the second stage bootloader from. Those bits can be controlled by the [[test_points#serial_header|serial header]]: shorting pad 2 to ground sets those bits to 0, enabling UART boot.
 +
 +Bit 19 is tied to pad N2 of the SoC. On the gamepad, it is tied to ground through R133 (zero-ohm resistor).
  
  
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 **0xF0000058** **0xF0000058**
 +
 +Hardware reset register.
  
 ^ Bits ^ Desc. ^ ^ Bits ^ Desc. ^
 | 0    | Reset IRQ controller | | 0    | Reset IRQ controller |
 | 1    | Reset timers | | 1    | Reset timers |
-| 2    | Reset RAM??? (displays static pattern) |+| 2    | Reset RAM? |
 | 3    | Reset DMA | | 3    | Reset DMA |
 | 4    | Reset SPI | | 4    | Reset SPI |
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 | 14   | Reset I2C4 | | 14   | Reset I2C4 |
 | 15   | Reset audio controller | | 15   | Reset audio controller |
-| 16   | Reset ??? (0xF0008400) |+| 16   | Reset H264 codec (0xF0008400) |
 | 17   | ??? | | 17   | ??? |
 | 18   | Reset ??? (0xF0008800, 0xF0008900) | | 18   | Reset ??? (0xF0008800, 0xF0008900) |
 | 19   | Reset ??? (0xF0008C00) | | 19   | Reset ??? (0xF0008C00) |
-| 20   | Reset ??? (0xF0009000) |+| 20   | Reset camera controller (0xF0009000) |
 | 21   | Reset LCD controller (0xF0009400, 0xF0009500, 0xF0009600, 0xF0009700) | | 21   | Reset LCD controller (0xF0009400, 0xF0009500, 0xF0009600, 0xF0009700) |
  
 Setting a bit to 1 then 0 resets the corresponding hardware component. This register is 22 bits wide. Setting a bit to 1 then 0 resets the corresponding hardware component. This register is 22 bits wide.
 +
 +Bit 2 is used by the boot ROM. Using it from code running in RAM will crash the gamepad. This bit might be for resetting RAM, but at the same time, the RAM does somewhat retain old data across consecutive boots, so it's not entirely clear how this works.
  
  
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 | 2      | ???               | ??? | | 2      | ???               | ??? |
 | 3      | 3.08 MHz          | Audio bit clock (from [[audio amplifier]]) | | 3      | 3.08 MHz          | Audio bit clock (from [[audio amplifier]]) |
-| 4      | 864 MHz           | Primary clock | +| 4      | 864 MHz           | PLL - Primary clock | 
-| 5      | 3.38 MHz          | Secondary clock 1 | +| 5      | 3.38 MHz          | PLL - Secondary clock 1 | 
-| 6      | 16 MHz            | Secondary clock 2 | +| 6      | 16 MHz            | PLL - Secondary clock 2 | 
-| 7      | 3.38 MHz          | Secondary clock 3 |+| 7      | 3.38 MHz          | PLL - Secondary clock 3 |
  
 Peripherals may then divide their incoming clocks further. For example, in the case of I2C, the clock is divided by 24 before being output to the SCL line. Peripherals may then divide their incoming clocks further. For example, in the case of I2C, the clock is divided by 24 before being output to the SCL line.
general_registers.1746800952.txt.gz · Last modified: 2025/05/09 14:29 by arisotura
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