Differences

This shows you the differences between two versions of the page.

--- general_registers [2025/05/08 20:57] – arisotura
+++ general_registers [2025/05/16 23:07] (current) – arisotura
@@ Line 48: / Line 48: @@
 x41 (MS01)
 |
-| 8-9   | ?? |
+| 8-15   | ?? |
-| 12    | BootROM disable |
 | 16    | SoC type; 0=DRC, 1=DRH |
 | 17-18 | Source for second stage bootloader; 0=UART1, 1=UART1, 2=SPI, 3=I2C |
@@ Line 60: / Line 59: @@
   * There may be other differences too
-Bits 8-9 are set at some point during the early boot process (observed value of 0x00040340).
+Bits 8-15 are writable when the boot ROM is running. They seem to become read-only after the boot ROM is disabled. They might just serve as software-defined boot flags.
-Bit 12 is set by the boot ROM before resetting the CPU. This bit cannot be cleared. It is likely the boot ROM disable flag.
+Bit 12 is set by the boot ROM before resetting the CPU.
 Bits 16 and 19 are checked during hardware initialization, to choose the correct PLL settings.
@@ Line 73: / Line 72: @@
   * Flash layout is also different, with firmware bank 2 being at 0x480000 instead of 0x500000
-The boot ROM checks bits 17-18 to determine where to load the second stage bootloader from. It is unknown whether those bits can be controlled externally.
+The boot ROM checks bits 17-18 to determine where to load the second stage bootloader from. Those bits can be controlled by the [[test_points#serial_header|serial header]]: shorting pad 2 to ground sets those bits to 0, enabling UART boot.
+Bit 19 is tied to pad N2 of the SoC. On the gamepad, it is tied to ground through R133 (zero-ohm resistor).
@@ Line 112: / Line 113: @@
 Soft reset register. Setting bit 0 to 0 then 1 resets the CPU after a short delay.
+This likely also disables the boot ROM overlay and makes bit 8-15 in register 0xF0000000 read-only.
+Weirdly, the boot ROM sets it to 1 without setting it to 0 first. This register might just react to 0-to-1 transitions.
 **0xF0000058**
+Hardware reset register.
 ^ Bits ^ Desc. ^
 | 0    | Reset IRQ controller |
 | 1    | Reset timers |
-| 2    | Reset RAM??? (displays static pattern) |
+| 2    | Reset RAM? |
 | 3    | Reset DMA |
 | 4    | Reset SPI |
@@ Line 133: / Line 140: @@
 | 14   | Reset I2C4 |
 | 15   | Reset audio controller |
-| 16   | Reset ??? (0xF0008400) |
+| 16   | Reset H264 codec (0xF0008400) |
 | 17   | ??? |
 | 18   | Reset ??? (0xF0008800, 0xF0008900) |
 | 19   | Reset ??? (0xF0008C00) |
-| 20   | Reset ??? (0xF0009000) |
+| 20   | Reset camera controller (0xF0009000) |
 | 21   | Reset LCD controller (0xF0009400, 0xF0009500, 0xF0009600, 0xF0009700) |
 Setting a bit to 1 then 0 resets the corresponding hardware component. This register is 22 bits wide.
+Bit 2 is used by the boot ROM. Using it from code running in RAM will crash the gamepad. This bit might be for resetting RAM, but at the same time, the RAM does somewhat retain old data across consecutive boots, so it's not entirely clear how this works.