WiiU Gamepad Technical Documentation

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general_registers

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general_registers [2025/04/17 19:54] – arisoturageneral_registers [2025/05/16 23:07] (current) – arisotura
Line 25: Line 25:
 | 0xF0000054 | Clocks - SDIO clock setting | | 0xF0000054 | Clocks - SDIO clock setting |
 | 0xF0000058 | Hardware reset | | 0xF0000058 | Hardware reset |
 +| 0xF000005C | ?? |
 | 0xF0000060 | ?? | | 0xF0000060 | ?? |
 | 0xF0000064 | ?? | | 0xF0000064 | ?? |
Line 47: Line 48:
   0x41 (MS01)   0x41 (MS01)
 | |
-| 8-15  | ?? | +| 8-15   | ?? | 
-| 16    | DRC base clock; 0=16MHz, 1=24MHz | +| 16    | SoC type; 0=DRC, 1=DRH | 
-| 17-18 | ? |+| 17-18 | Source for second stage bootloader; 0=UART1, 1=UART1, 2=SPI, 3=I2C |
 | 19    | Type of PLL? | | 19    | Type of PLL? |
  
Line 57: Line 58:
   * There are also differences in the video decoder and LCD controller   * There are also differences in the video decoder and LCD controller
   * There may be other differences too   * There may be other differences too
 +
 +Bits 8-15 are writable when the boot ROM is running. They seem to become read-only after the boot ROM is disabled. They might just serve as software-defined boot flags.
 +
 +Bit 12 is set by the boot ROM before resetting the CPU.
  
 Bits 16 and 19 are checked during hardware initialization, to choose the correct PLL settings. Bits 16 and 19 are checked during hardware initialization, to choose the correct PLL settings.
  
-Bit 16 seems to denote different hardware, additionally to the different base clock: +The boot ROM and bootloader seem to be the same for both DRC (gamepad SoC) and DRH (WiiU side SoC). 
-  * when it is set, the bootloader doesn't interact with the UIC at all (otherwise it sends the 0x7F sync command and retrieves the UIC state if possible)+ 
 +Notably, when bit 16 is set: 
 +  * slightly different PLL settings are used -- the input clock is 24 MHz instead of 16 MHz 
 +  * the bootloader doesn't interact with the UIC at all (otherwise it sends the 0x7F sync command and retrieves the UIC state if possible)
   * Flash layout is also different, with firmware bank 2 being at 0x480000 instead of 0x500000   * Flash layout is also different, with firmware bank 2 being at 0x480000 instead of 0x500000
  
 +The boot ROM checks bits 17-18 to determine where to load the second stage bootloader from. Those bits can be controlled by the [[test_points#serial_header|serial header]]: shorting pad 2 to ground sets those bits to 0, enabling UART boot.
 +
 +Bit 19 is tied to pad N2 of the SoC. On the gamepad, it is tied to ground through R133 (zero-ohm resistor).
 +
 +
 +===== Hardware setup =====
 +
 +**0xF0000008**
 +
 +Unknown.
 +
 +^ Bits ^ Desc. ^
 +| 0    | ??? |
 +| 1    | ??? |
 +| 2    | ??? |
 +| 3    | ??? |
 +| 4    | ??? |
 +
 +
 +**0xF0000030**
 +
 +Probably related to clock generation?
 +
 +^ Bits ^ Desc. ^
 +| 0    | ??? |
 +| 1    | ??? important |
 +| 8    | ??? |
 +| 9    | ??? |
 +| 10   | ??? setting this bit crashes gamepad |
 +
 +
 +**0xF0000064**
 +
 +Unknown. Probably related to clock stuff. Set to 6 on gamepad, 9 on DRH. Coincidentally, 9/6 = 24/16 = 1.5.
  
  
Line 71: Line 113:
  
 Soft reset register. Setting bit 0 to 0 then 1 resets the CPU after a short delay. Soft reset register. Setting bit 0 to 0 then 1 resets the CPU after a short delay.
 +
 +This likely also disables the boot ROM overlay and makes bit 8-15 in register 0xF0000000 read-only.
 +
 +Weirdly, the boot ROM sets it to 1 without setting it to 0 first. This register might just react to 0-to-1 transitions.
  
  
 **0xF0000058** **0xF0000058**
 +
 +Hardware reset register.
  
 ^ Bits ^ Desc. ^ ^ Bits ^ Desc. ^
 | 0    | Reset IRQ controller | | 0    | Reset IRQ controller |
 | 1    | Reset timers | | 1    | Reset timers |
-| 2    | Reset RAM??? (displays static pattern) |+| 2    | Reset RAM? |
 | 3    | Reset DMA | | 3    | Reset DMA |
 | 4    | Reset SPI | | 4    | Reset SPI |
Line 92: Line 140:
 | 14   | Reset I2C4 | | 14   | Reset I2C4 |
 | 15   | Reset audio controller | | 15   | Reset audio controller |
-| 16   | Reset ??? (0xF0008400) |+| 16   | Reset H264 codec (0xF0008400) |
 | 17   | ??? | | 17   | ??? |
 | 18   | Reset ??? (0xF0008800, 0xF0008900) | | 18   | Reset ??? (0xF0008800, 0xF0008900) |
 | 19   | Reset ??? (0xF0008C00) | | 19   | Reset ??? (0xF0008C00) |
-| 20   | Reset ??? (0xF0009000) |+| 20   | Reset camera controller (0xF0009000) |
 | 21   | Reset LCD controller (0xF0009400, 0xF0009500, 0xF0009600, 0xF0009700) | | 21   | Reset LCD controller (0xF0009400, 0xF0009500, 0xF0009600, 0xF0009700) |
  
 Setting a bit to 1 then 0 resets the corresponding hardware component. This register is 22 bits wide. Setting a bit to 1 then 0 resets the corresponding hardware component. This register is 22 bits wide.
 +
 +Bit 2 is used by the boot ROM. Using it from code running in RAM will crash the gamepad. This bit might be for resetting RAM, but at the same time, the RAM does somewhat retain old data across consecutive boots, so it's not entirely clear how this works.
  
  
Line 106: Line 156:
 The gamepad starts at a clock of 16 MHz. PLL settings applied by the second stage bootloader change the system clock to 108 MHz. The gamepad starts at a clock of 16 MHz. PLL settings applied by the second stage bootloader change the system clock to 108 MHz.
  
-Different settings are applied based on the base clock - it appears that some prototype versions use a base clock of 24 MHz. +Different settings are applied based on the base clock. 
  
 ^ Setting    ^ 16 MHz value ^ 24 MHz value ^ ^ Setting    ^ 16 MHz value ^ 24 MHz value ^
general_registers.1744919674.txt.gz · Last modified: 2025/04/17 19:54 by arisotura
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