general_registers
Differences
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| Both sides previous revisionPrevious revision | |||
| general_registers [2025/05/16 23:07] – arisotura | general_registers [2025/10/15 21:16] (current) – arisotura | ||
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| | 2 | ??? | ??? | | | 2 | ??? | ??? | | ||
| | 3 | 3.08 MHz | Audio bit clock (from [[audio amplifier]]) | | | 3 | 3.08 MHz | Audio bit clock (from [[audio amplifier]]) | | ||
| - | | 4 | 864 MHz | Primary clock | | + | | 4 | 864 MHz |
| - | | 5 | 3.38 MHz | Secondary clock 1 | | + | | 5 | 3.38 MHz | PLL - Secondary clock 1 | |
| - | | 6 | 16 MHz | Secondary clock 2 | | + | | 6 | 16 MHz | PLL - Secondary clock 2 | |
| - | | 7 | 3.38 MHz | Secondary clock 3 | | + | | 7 | 3.38 MHz | PLL - Secondary clock 3 | |
| Peripherals may then divide their incoming clocks further. For example, in the case of I2C, the clock is divided by 24 before being output to the SCL line. | Peripherals may then divide their incoming clocks further. For example, in the case of I2C, the clock is divided by 24 before being output to the SCL line. | ||
general_registers.txt · Last modified: 2025/10/15 21:16 by arisotura