Differences

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--- camera_controller [2025/04/16 21:05] – arisotura
+++ camera_controller [2025/05/17 11:50] (current) – arisotura
@@ Line 1: / Line 1: @@
 ====== Camera controller ======
-NOTE: this is a findings dump for now. It is unclear what is what, so there may be stuff pertaining to the h265 codec in here. Not sure how interwoven it is with the camera controller.
+NOTE: this is a findings dump for now. It is unclear what is what, so there may be stuff pertaining to the h264 codec in here. Not sure how interwoven it is with the camera controller.
 Known registers:
@@ Line 7: / Line 7: @@
 ^ Address    ^ Desc. ^
 | 0xF0000800 | ??? (might not be strictly camera-related) |
-| ||
+| 0xF0000818 | address for ??? |
-| 0xF0008414 | ??? |
+| 0xF000081C | Base address for processed camera buffer |
-| 0xF0008420 | ??? |
+| 0xF0000820 | Base address for third buffer?? |
-| 0xF0008468 | IRQ status/ack for IRQ 0x11 |
+| 0xF0000824 | Base address for raw camera buffer |
-| 0xF0008474 | ??? |
+| 0xF0000828 | ??? set to same as F000081C |
-| 0xF0008478 | ??? IRQ enable flags?? |
+| 0xF000082C | ??? set to 0x400000 |
-| 0xF00084B0 | ??? |
 | ||
 | 0xF0008800 | ??? |
@@ Line 33: / Line 32: @@
 | 0xF0008C34 | ??? |
 | 0xF0008C70 | IRQ status/ack for IRQ 0x10 |
+| 0xF0008C74 | ??? related to IRQ 0x10? |
 | ||
 | 0xF0009000 | ??? control register? |
@@ Line 47: / Line 47: @@
 ^ IRQ  ^ Desc. ^
-| 0x10 | ??? |
+| 0x10 | camera processing? |
-| 0x11 | data ready? |
+| 0x14 | Camera event |
-| 0x14 | ??? |
 | 0x1D | ??? |
+The camera controller can write output to atleast three different buffers:
+  * Raw camera buffer, that is, picture data straight out of the camera
+  * Processed camera buffer, picture data going through extra processing (round-trip through H264 codec?)
+  * Third buffer, not known for what
@@ Line 60: / Line 64: @@
 ^ IRQ bit ^ Desc. ^
-| 0       | Vertical IRQ |
+| 0       | Camera frame IRQ |
 | 1       | ??? |
 | 2       | ??? |
@@ Line 71: / Line 75: @@
 IRQ 1, 2 and 5 are unused by the stock firmware.
-IRQ 0 fires at the position specified by register 0xF00094F8 plus 8 scanlines.
+IRQ 0 fires between each camera frame. It can be synchonized to the display with [[LCD controller|register 0xF00094F8]]. TODO: not known if it marks the start or end of the camera VBlank; it is probably the end, ie. the start of a new camera frame.
 These IRQ conditions are connected to IRQ 0x14.
+===== Camera video format =====
+The video data produced by the camera is YUV, encoded in a NV12-like interleaved format.
+The data is split in chunks of 48 bytes. In each chunk, the first 16 bytes are Y values for a row of 16 pixels, the next 16 bytes are Y values for the next row (underneath the first row), the next 8 bytes are U values, and the last 8 bytes are V values. U/V value pairs are shared across blocks of 2x2 pixels.
+Oddly, it seems that in each row, the values are stored backwards, and this regardless of the camera's mirror setting.
+The camera can produce data in other formats, but it's not yet known how they work. Also unknown if the controller supports different encodings.
+===== Camera timings =====
+The camera VSync is generated by the SoC's camera controller, rather than by the camera itself. It seems that the pixel clock is also generated by the SoC, but the HREF signal (horizontal sync) is generated by the camera.
+When the camera is active, its input clock ([[General registers|register 0xF0000038]]) is set to 24 MHz. The camera then divides that clock by 2. These settings are suitable for a framerate of 30 FPS at 640x480.
+It is possible to reach 60 FPS at 640x480 by either doubling the input clock or changing the camera's clock divider to 1 (instead of 2), but doing so seems to produce a picture with weird colors. Possibly other settings need to be adjusted as well, like the exposure time, etc...
+When the camera is inactive, the input clock is set to ~125.5 KHz, presumably to save energy.