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IRQ controller
The IRQ controller is presumably able to schedule and distribute IRQs based on a priority order.
Registers
The IRQ controller has the following registers:
| Address | Desc. |
|---|---|
| 0xF0001200 | Shorthand IRQ enable for IRQ 0x00..0x0F |
| 0xF0001204 | Shorthand IRQ enable for IRQ 0x10..0x1F |
| 0xF0001208+(N*4) | IRQ enable for IRQ N |
| 0xF00013F0 | Current IRQ index |
| 0xF00013F8 | IRQ priority mask and acknowledge |
| 0xF00013FC | IRQ priority mask read and clear |
| 0xF0001420+(N*4) | IRQ trigger type for IRQ N |
| 0xF00019D8 | General IRQ enable? |
| 0xF00019DC | Unknown, set to 0 |
| 0xF00019F8 | Read-only mirror of 0xF00013F8 |
| 0xF00019FC | Read-only mirror of 0xF00013FC |
Stock firmware tries to initialize registers 0xF0001520..0xF000153C. These registers don't seem to actually exist. Likely, this is a mistake, and that code was intended to access registers 0xF00014A0..0xF00014BC.
0xF0001200
Shorthand IRQ enable for IRQ 0x00..0x0F.
Bits 0..15 correspond to IRQ 0x00..0x0F respectively. A 0 bit enables an IRQ, a 1 bit disables it.
Changing this register changes bit 6 in the corresponding IRQs' enable registers, and vice versa. This register is useful for quickly enabling or disabling multiple IRQs in a row.
0xF0001204
Shorthand IRQ enable for IRQ 0x10..0x1F.
Function same as 0xF0001200.
0xF0001208+(N*4)
IRQ enable.
| Bits | Desc. |
|---|---|
| 0-3 | Presumably priority |
| 6 | IRQ disable; 0=enable, 1=disable |
0xF00013F0
Index of the source of the IRQ currently being serviced.
When there is a pending IRQ, reading from this register resets the IRQ priority mask at 0xF00013F8 to zero, effectively masking out all interrupts until the current interrupt is handled.
Reads as 0x80 when there is no pending IRQ.
0xF00013F8
4-bit IRQ priority “mask”. Actually a number that masks out interrupts with priority equal to or above it. 0xF is the lightest setting, which only masks out priority 0xF.
This register is copied to 0xF00013FC upon IRQ.
Writing to this register also acknowledges the current interrupt.
0xF00013FC
4-bit IRQ priority “mask” read and clear. This value is meant to be written back to 0xF00013F8 once the current interrupt is handled.
This register is read-only.
0xF0001420+(N*4)
Affects the way each IRQ is triggered, but it is not yet known in which way exactly. Observed values are 1 and 5.
Some IRQ sources will not function correctly without the correct trigger type. For example, VBlank IRQs will only fire once if their trigger type is set to 5.
0xF00019D8
Initialized to 1. Setting to 0 disables interrupts.
0xF00019DC
Initialized to 0. Setting to 1 disables interrupts.
0xF00019F8
Read-only mirror of 0xF00013F8.
0xF00019FC
Mirror of 0xF00013FC.
IRQ sources
Here are the indexes of the possible IRQ sources, and the settings the stock firmware assigns them:
| IRQ index | Trigger | Desc. |
|---|---|---|
| 0x00 | 1 | Timer 0 |
| 0x01 | 1 | Timer 1 |
| 0x02 | 1 | SDIO |
| 0x03 | 5 | ??? |
| 0x04 | 5 | ??? |
| 0x05 | 5 | UART |
| 0x06 | 5 | SPI |
| 0x07 | 5 | SPI related? |
| 0x08 | 1 | DMA0 |
| 0x09 | 1 | DMA1 |
| 0x0A | 1 | ??? |
| 0x0B | 1 | ??? |
| 0x0C | 1 | DMA4 |
| 0x0D | 1 | DMA2 |
| 0x0E | 1 | DMA3 |
| 0x0F | 5 | I2C |
| 0x10 | 5 | vcapt/camera |
| 0x11 | 5 | vcapt/camera |
| 0x12 | 5 | vout |
| 0x13 | 5 | ??? |
| 0x14 | 5 | vcapt/camera |
| 0x15 | 1 | VBlank end |
| 0x16 | 1 | VBlank start |
| 0x17 | 5 | Audio output event |
| 0x18 | 5 | Audio input event |
| 0x19 | 5 | ??? |
| 0x1A | 5 | ??? |
| 0x1B | 5 | ??? |
| 0x1C | 5 | ??? |
| 0x1D | 5 | vcapt/camera |
| 0x1E | 1 | VCount match |
| 0x1F | 1 | ??? |
| 0x20 | 1? | ??? |
| 0x21 | 1? | ??? |
| 0x22 | 1? | ??? |
| 0x23 | 1? | ??? |
| 0x24 | 1? | ??? |
| 0x25 | 1? | ??? |
| 0x26 | 1? | ??? |
| 0x27 | 1? | ??? |
Unknown what IRQ 0x20..0x27 would be; software IRQs maybe? They are different (they don't seem to have priority bits for one).