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h264_codec

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H264 codec

The gamepad features a hardware H264 codec. It can decode a video feed to the screen, and encode the video feed from the camera.

Register map:

Address Desc.
0xF0008414 ???
0xF0008420 ???
0xF0008460 Encoding buffer alert position
0xF0008464 Encoding buffer current position
0xF0008468 Encoding IRQ status/ack/disable
0xF000846C Encoding buffer start
0xF0008470 Encoding buffer end
0xF0008474 Encoding buffer alert offset
0xF0008478 ???
0xF000847C Encoding buffer frame position
0xF00084A4 buffer address for incoming h265 data?
0xF00084A8 another buffer address?
0xF00084AC ??? buffer? position?
0xF00084B0 Decoding IRQ status/ack
0xF00084B8 ???

Related IRQs:

IRQ Desc.
0x11 Encoding event
0x12 Decoding event

Encoding

The encoder side receives video data from the camera, encodes it, and writes the H264 bitstream to RAM.

TODO: figure out what enables/disables the encoder/decoder

TODO: figure out alignment requirements for the various buffer registers

0xF0008460

Encoding buffer alert position.

IRQ 0 fires as long as the current buffer position is greater or equal to this register.

This register is 24 bits wide.

0xF0008464

Encoding buffer current position.

This register keeps track of where the encoder is writing new data within its buffer. It is read-only.

This register is 24 bits wide.

0xF0008468

Encoding IRQ status, acknowledge, and disable.

Bits 0-7 are IRQ status flags. Bits 8-15 are IRQ acknowledge flags, ie. writing a 1 to a bit acknowledges the corresponding IRQ. Bits 16-23 are IRQ disable flags, ie. setting a bit to 1 disables the corresponding IRQ.

Due to the all-in-one nature of this register, one should avoid overwriting the disable flags when acknowledging an IRQ (ie. by ORing the register with the desired IRQ ack bitmask).

The IRQ bits are as follows:

IRQ bit Desc.
0 Position alert IRQ
1 Frame IRQ
2 ???
3 ??
4-7 ???

IRQ 0 fires when the current buffer position reaches the alert position. When acknowledging this IRQ, the alert position should be updated, otherwise the IRQ will keep firing as long as the condition is met.

IRQ 1 fires every time a full camera frame is encoded. Register 0xF000847C keeps track of where the frame ends in the encoding buffer.

IRQ 3 will fire repeatedly under certain conditions, not sure which.

I haven't observed other IRQs yet.

0xF000846C

Encoding buffer start address.

This register is 24 bits wide.

0xF0008470

Encoding buffer end address.

When the current buffer position reaches this address, it loops back to the start address.

This register is 24 bits wide.

0xF0008474

Encoding buffer alert offset.

This register is added to register 0xF0008460 when checking for the alert IRQ. It is typically set to the desired chunk length (for repeating the IRQ per a given chunk size).

Setting this register to zero disables the position alert IRQ.

This register is 24 bits wide.

0xF000847C

Encoding buffer frame position.

Bits Desc.
0-23 Frame position (memory address)
24-31 ???

Upon IRQ 1, this register points to the end of the frame that was just finished. It seems to be readable once, becoming zero after it has been read.

h264_codec.1747434654.txt.gz · Last modified: 2025/05/16 22:30 by arisotura

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