IRQ controller

The IRQ controller is presumably able to schedule and distribute IRQs based on a priority order.

The IRQ controller has the following registers:

0xF0001208+(N*4)

IRQ enable.

0xF00013F0

Index of the source of the IRQ currently being serviced.

When there is a pending IRQ, reading from this register resets the IRQ priority mask at 0xF00013F8 to zero, effectively masking out all interrupts until the current interrupt is handled.

Reads as 0x80 when there is no pending IRQ.

0xF00013F8

4-bit IRQ priority “mask”. Actually a number that masks out interrupts with priority equal to or above it. 0xF is the lightest setting, which only masks out priority 0xF.

This register is copied to 0xF00013FC upon IRQ.

Writing to this register also acknowledges the current interrupt.

0xF00013FC

4-bit IRQ priority “mask” read and clear. This value is meant to be written back to 0xF00013F8 once the current interrupt is handled.

This register is read-only.

0xF0001420+(N*4)

Affects the way each IRQ is triggered, but it is not yet known in which way exactly. Observed values are 1 and 5.

Some IRQ sources will not function correctly without the correct trigger type. For example, VBlank IRQs will only fire once if their trigger type is set to 5.

0xF00019D8

Possibly general IRQ enable. Initialized to 1.

0xF00019DC

Unknown. Initialized to 0.

0xF00019F8

Read-only mirror of 0xF00013F8.

0xF00019FC

Mirror of 0xF00019FC.

Here are the indexes of the possible IRQ sources, and the settings the stock firmware assigns them: