WiiU Gamepad Technical Documentation

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====== I2C ======

The I2C interface connects the LCD, audio amplifier and camera to the CPU.

There are two possible I2C controllers. If the LSB of [[General registers|register 0xF0000000]] is 0x41, the gamepad has the Samsung controller, otherwise it has the Renesas controller.

In practice, I have only seen Renesas controllers so far, so I don't know how rare the Samsung one is. Considering that the I2C controller is part of the SoC, it is likely that the Samsung controller is solely prototype stuff. As further evidence, the diagnostics firmware only supports the Renesas controller.

There are 5 I2C busses, referred to as 0, 1, 2, 3 and 4. Busses 0 and 1 appears to be for slave mode, while the others are for master mode. In practice, all the I2C devices are on bus 3, leaving the others unused. It isn't even known if the other busses have any connections outside of the DRC SoC. Busses 2 and 4 are nonfunctional.

The I2C registers are distributed as follows:
^ Base address ^ Desc. ^
| 0xF0005800   | General I2C registers and bus 0 |
| 0xF0005C00   | Bus 1 |
| 0xF0006000   | Bus 2 |
| 0xF0006400   | Bus 3 |
| 0xF0006800   | Bus 4 |


===== General registers =====

These registers control the individual busses.

^ Address    ^ Desc. ^
| 0xF0005800 | IRQ flags |
| 0xF0005804 | IRQ enable |
| 0xF0005808 | IRQ acknowledge |

In each register, bit0..4 corresponds to bus 0..4.


===== Renesas controller =====

==== Slave mode (bus 0..1) ====

^ Offset ^ Desc. ^
| 0x104  | ?? |
| 0x108  | ?? |
| 0x138  | Data 0 |
| 0x13C  | Data 1 |


==== Master mode (bus 2..4) ====

^ Offset ^ Desc. ^
| 0x000  | ??? |
| 0x004  | Data input/output |
| 0x008  | Transfer control |
| 0x010  | ??? |
| 0x018  | Transfer status |
| 0x020  | Status register? |


**0xF0006x04**

Data input/output.


**0xF0006x08**

Transfer control.

^ Bits ^ Desc. ^
| 0    | Stop |
| 1    | Start |
| 2    | Read mode? Ack? |
| 3    | Write mode |
| 4    | Enable transfer |
| 5    | Request data (when reading) |

Bit 0 appears to be write-only.

Bit 5 gets cleared after a data byte is received.

TODO: bit 5 is also set at the end of a read??

During a read transfer, the controller seems to automatically know when to send a NACK.


**0xF0006x18**

Transfer status.

^ Bits ^ Desc. ^
| 0    | Stop generated  |
| 1    | Start generated |
| 2    | Ack (from remote) |
| 3    | Direction; 0=reading, 1=writing |
| 7    | Transfer pending |


**0xF0006x20**

Status register of sorts.

^ Bits ^ Desc. ^
| 0    | ??? |
| 1    | ??? gets cleared |
| 6    | Transfer pending |
| 7    | ??? |


===== Samsung controller =====

==== Slave mode (bus 1) ====

TODO


==== Master mode (bus 2..4) ====

^ Offset ^ Desc. ^
| 0x000  | Transfer control?? |
| 0x004  | ?? |
| 0x00C  | Data input/output |
| 0x010  | ?? |


===== I2C devices =====

The following devices are connected to the I2C interface:
^ Bus ^ Device ID ^ Device ^
| 3   | 0x18      | [[Audio amplifier]] |
| 3   | 0x21      | Camera |
| 3   | 0x39      | [[LCD]] |