uart
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| uart [2025/04/19 18:37] – arisotura | uart [2025/05/10 11:55] (current) – arisotura | ||
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| Data output. | Data output. | ||
| - | Data received can be read out from this register. | + | Data received can be read out from this register. If data is received while the FIFO is already full, the RX error IRQ is raised. |
| Line 55: | Line 55: | ||
| **Base+0x08** | **Base+0x08** | ||
| + | |||
| + | IRQ enable. | ||
| ^ Bits ^ Desc. ^ | ^ Bits ^ Desc. ^ | ||
| | 0 | Enable RX IRQ (4) | | | 0 | Enable RX IRQ (4) | | ||
| | 1 | Enable TX IRQ (2) | | | 1 | Enable TX IRQ (2) | | ||
| - | | 2 | Enable RX fail IRQ (6) | | + | | 2 | Enable RX error IRQ (6) | |
| Line 78: | Line 80: | ||
| IRQ 4 is fired when a byte of data is received. To acknowledge it, read the data from the data output port. | IRQ 4 is fired when a byte of data is received. To acknowledge it, read the data from the data output port. | ||
| - | IRQ 6 is fired when data reception fails. For example this happens if the RX line is pulled low (when polarity set to active high). The only known way to acknowledge this IRQ is to reset the UART entirely. | + | IRQ 6 is fired when data reception fails. For example this happens if the RX line is pulled low (when polarity set to active high). This also happens on parity errors. The only known way to acknowledge this IRQ is to reset the UART entirely. |
| - | Unknown what IRQ 12 would be, maybe parity error? | + | Unknown what IRQ 12 would be. Firmware code has a case for it, but I haven' |
| Line 103: | Line 105: | ||
| | 0 | RX FIFO not empty | | | 0 | RX FIFO not empty | | ||
| | 1 | RX FIFO overflow (received data while FIFO already full) | | | 1 | RX FIFO overflow (received data while FIFO already full) | | ||
| + | | 2 | RX parity error | | ||
| + | | 3 | RX error, ? (FIFO overflow?) | | ||
| | 4 | RX line error (ie. line held low) | | | 4 | RX line error (ie. line held low) | | ||
| | 5 | 1 when ready to send, 0 when sending | | | 5 | 1 when ready to send, 0 when sending | | ||
| Line 132: | Line 136: | ||
| ^ Bits ^ Desc. ^ | ^ Bits ^ Desc. ^ | ||
| | 0 | Enable UART | | | 0 | Enable UART | | ||
| - | | 1 | Bit order; 0=LSb first, 1=MSb first | | + | | 1 | Data bit order; 0=LSb first, 1=MSb first | |
| | 2 | Line polarity; 0=active high, 1=active low | | | 2 | Line polarity; 0=active high, 1=active low | | ||
| Line 143: | Line 147: | ||
| ^ Bits ^ Desc. ^ | ^ Bits ^ Desc. ^ | ||
| - | | 0-2 | RX state | | + | | 0-3 | RX state | |
| | 8-12 | RX FIFO level (occupied space, 0..16) | | | 8-12 | RX FIFO level (occupied space, 0..16) | | ||
| Line 151: | Line 155: | ||
| * 2 = receiving data bit | * 2 = receiving data bit | ||
| * 7 = waiting for next data bit? | * 7 = waiting for next data bit? | ||
| - | * 4 = receiving stop bit | + | * 3 = receiving |
| + | * 8 = checking parity bit? | ||
| + | * 9 = waiting for stop bits after parity | ||
| + | * 4 = receiving stop bits | ||
| * 10 = storing byte into FIFO | * 10 = storing byte into FIFO | ||
| * 0 = idle | * 0 = idle | ||
| Line 161: | Line 168: | ||
| ^ Bits ^ Desc. ^ | ^ Bits ^ Desc. ^ | ||
| - | | 0-2 | TX state | | + | | 0-3 | TX state | |
| | 8-12 | TX FIFO level (occupied space, 0..16) | | | 8-12 | TX FIFO level (occupied space, 0..16) | | ||
| Line 168: | Line 175: | ||
| * 1 = sending start bit | * 1 = sending start bit | ||
| * 2 = sending data bits | * 2 = sending data bits | ||
| - | * 4 = sending stop bit | + | |
| + | | ||
| * 0 = idle | * 0 = idle | ||
| Line 177: | Line 185: | ||
| ^ Bits ^ Desc. ^ | ^ Bits ^ Desc. ^ | ||
| - | | 0-4 | ??? | | + | | 0-3 | ??? | |
| + | | 4 | Aux. LED (for UART2) (0=off, 1=on) | | ||
| | 8-14 | ??? | | | 8-14 | ??? | | ||
| Line 194: | Line 203: | ||
| The input clock can be configured in the [[General registers|clock registers]]. Each UART gets its own clock register: 0xF0000040 for UART0, 0xF0000044 for UART1, and 0xF0000048 for UART2. | The input clock can be configured in the [[General registers|clock registers]]. Each UART gets its own clock register: 0xF0000040 for UART0, 0xF0000044 for UART1, and 0xF0000048 for UART2. | ||
| + | |||
| + | Here is a table of settings for common baud rates, given an input clock of 16 MHz: | ||
| + | |||
| + | ^ Baud rate ^ Divider 1 ^ Multiplier ^ Divider 2 ^ | ||
| + | | 4800 | 1 | 3 | 625 | | ||
| + | | 9600 | 1 | 6 | 625 | | ||
| + | | 19200 | 1 | 12 | 625 | | ||
| + | | 38400 | 1 | 24 | 625 | | ||
| + | | 57600 | 1 | 36 | 625 | | ||
| + | | 115200 | ||
| + | | 230400 | ||
| + | | 460800 | ||
| + | | 921600 | ||
| The diagnostics firmware contains code (at 0xAC0EE) to calculate the multiplier/ | The diagnostics firmware contains code (at 0xAC0EE) to calculate the multiplier/ | ||
| Line 245: | Line 267: | ||
| Output '' | Output '' | ||
| + | |||
| + | ===== Using with DMA ===== | ||
| + | |||
| + | Much like SPI, the UARTs can be used conjointly with [[DMA]] channels 0 or 1. | ||
| + | |||
| + | To send data using DMA, you simply start a write DMA transfer instead of manually writing data to the UART's data output port. You should rely on the TX IRQ (2) to detect transfer completion. | ||
| + | |||
| + | To receive data using DMA, you can start a read DMA transfer at any moment. The DMA transfer will complete when the requested amount of bytes has been received. Note that if a read DMA transfer is active on the UART, it will suppress the RX IRQ. Thus, you should rely on the DMA completion IRQ to detect transfer completion. | ||
uart.1745087836.txt.gz · Last modified: 2025/04/19 18:37 by arisotura