Differences

This shows you the differences between two versions of the page.

--- spi [2025/03/03 11:26] – arisotura
+++ spi [2025/04/17 15:44] (current) – arisotura
@@ Line 17: / Line 17: @@
 | 0xF000440C | FIFO status |
 | 0xF0004410 | Data input/output |
-| 0xF0004414 | ?? |
+| 0xF0004414 | SPI low-level control |
 | 0xF0004418 | IRQ enable |
 | 0xF0004420 | Number of bytes to read |
@@ Line 30: / Line 30: @@
 | 0-2  | Clock source |
 | 3-10 | Clock divider |
+| 11-14 | ?? |
 | 15   | SPI enable (possibly just clock enable) |
@@ Line 112: / Line 113: @@
 **0xF0004414**
-Unknown. Bits 0-1, 4, 15 set by firmware code.
+Controls low-level aspects of the SPI protocol.
+^ Bits ^ Desc. ^
+| 0    | CPHA - Clock phase |
+| 1    | CPOL - Clock polarity; 0=invert source clock, 1=use source clock as-is |
+| 4    | ?? |
+| 15   | ?? |
+Clearing bit 15 has weird effects: seems to force CPOL to 1? This causes the transmitted data to be offset by one bit unless CPHA is 1.