Differences

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--- spi [2025/01/11 20:09] – arisotura
+++ spi [2025/04/17 15:44] (current) – arisotura
@@ Line 17: / Line 17: @@
 | 0xF000440C | FIFO status |
 | 0xF0004410 | Data input/output |
-| 0xF0004414 | ?? |
+| 0xF0004414 | SPI low-level control |
 | 0xF0004418 | IRQ enable |
 | 0xF0004420 | Number of bytes to read |
@@ Line 28: / Line 28: @@
 ^ Bits ^ Desc. ^
-| 0-2  | Clock multiplier |
+| 0-2  | Clock source |
 | 3-10 | Clock divider |
+| 11-14 | ?? |
 | 15   | SPI enable (possibly just clock enable) |
-The clock multiplier selects the base clock, and the clock divider divides that by a fixed value to produce the final SPI clock.
+The clock source selects the base clock, and the clock divider divides that by a fixed value to produce the final SPI clock.
-The following clock multiplier values are available:
+The clock source and divider values work the same way as in the [[General registers#Per-module clock settings|per-module clock setting registers]].
-^ Multiplier ^ Clock ^
-| 0          | 32MHz |
-| 1          | 12MHz |
-| 2          | ???   |
-| 3          | ???   |
-| 4          | ~857MHz |
-| 5          | 3.38MHz |
-| 6          | 15.9MHz |
-| 7          | 3.38MHz |
-Not sure how these values are generated internally. I couldn't get settings 2 and 3 to produce any observable output even at the highest divider setting. Setting 4 only works at low enough divider settings, and suggests that some kind of PLL is used. Not sure if the input clock is dependent on the system clock.
-The clock divider setting is a simple count-up divider. For example, setting it to 31 divides the clock by 32.
 Observed settings in the stock firmware are the following:
-^ Register value ^ Destination ^ Clock speed ^
+^ Register value ^ Destination ^ Clock speed  ^
-| 0x808C         | FLASH       | 48MHz       |
+| 0x808C         | FLASH       | 48 MHz       |
-| 0x8018         | UIC         | 8MHz        |
+| 0x8018         | UIC         | 8 MHz        |
-| 0x835C         | UIC         | 8MHz        |
+| 0x835C         | UIC         | 8 MHz        |
-| 0x83F8         | UIC         | 250KHz      |
+| 0x83F8         | UIC         | 250 KHz      |
-| 0x8400         | UIC         | 248KHz      |
+| 0x8400         | UIC         | 248 KHz      |
@@ Line 116: / Line 104: @@
 WARNING: if the write FIFO is already full, writes to this register are discarded. There seems to be no error signal in this case, so you have to be mindful of this.
-In a similar vein, a read transfer will halt if the read FIFO is full.
+In a similar vein, a read transfer will halt if the read FIFO is full (and resume when it is no longer full).
 Using [[DMA]] takes care of this automatically, avoiding many potential problems.
@@ Line 125: / Line 113: @@
 **0xF0004414**
-Unknown. Bits 0-1, 4, 15 set by firmware code.
+Controls low-level aspects of the SPI protocol.
+^ Bits ^ Desc. ^
+| 0    | CPHA - Clock phase |
+| 1    | CPOL - Clock polarity; 0=invert source clock, 1=use source clock as-is |
+| 4    | ?? |
+| 15   | ?? |
+Clearing bit 15 has weird effects: seems to force CPOL to 1? This causes the transmitted data to be offset by one bit unless CPHA is 1.