irq_controller
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irq_controller [2025/04/17 18:12] – arisotura | irq_controller [2025/05/16 22:33] (current) – arisotura | ||
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In practice, some IRQ lines likely stay active only for a very short time, while others will stay active as long as the underlying IRQ conditions are met (ie. from hardware components that have their own IRQ status registers; the IRQ line may stay active until the IRQ status register is cleared). | In practice, some IRQ lines likely stay active only for a very short time, while others will stay active as long as the underlying IRQ conditions are met (ie. from hardware components that have their own IRQ status registers; the IRQ line may stay active until the IRQ status register is cleared). | ||
- | IRQ trigger type 1 seems to detect a rising edge in the IRQ line, but the IRQ controller fails to fully process and signal | + | IRQ trigger type 5 seems to fail to register an interrupt when the pulse is too short (ie. doesn' |
The trigger type might also play a role in whether/how the IRQ line is buffered or treated? Values 0-7 are possible. Different values affect the different bits (8/ | The trigger type might also play a role in whether/how the IRQ line is buffered or treated? Values 0-7 are possible. Different values affect the different bits (8/ | ||
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| 0x01 | 1 | Timer 1 | | | 0x01 | 1 | Timer 1 | | ||
| 0x02 | 1 | SDIO | | | 0x02 | 1 | SDIO | | ||
- | | 0x03 | 5 | UART0? | | + | | 0x03 | 5 | UART0 | |
| 0x04 | 5 | UART1 | | | 0x04 | 5 | UART1 | | ||
| 0x05 | 5 | UART2 | | | 0x05 | 5 | UART2 | | ||
Line 144: | Line 144: | ||
| 0x0F | 5 | I2C | | | 0x0F | 5 | I2C | | ||
| 0x10 | 5 | vcapt/ | | 0x10 | 5 | vcapt/ | ||
- | | 0x11 | 5 | + | | 0x11 | 5 |
- | | 0x12 | 5 | + | | 0x12 | 5 |
| 0x13 | 5 | ??? | | | 0x13 | 5 | ??? | | ||
- | | 0x14 | 5 | + | | 0x14 | 5 |
| 0x15 | 1 | VBlank end | | | 0x15 | 1 | VBlank end | | ||
| 0x16 | 1 | VBlank start | | | 0x16 | 1 | VBlank start | |
irq_controller.1744913565.txt.gz · Last modified: 2025/04/17 18:12 by arisotura