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gpio [2025/05/13 11:35] arisoturagpio [2025/05/13 11:38] (current) arisotura
Line 56: Line 56:
 | 0xF0005104 | 0xFF01 | 0xC300  | DRC SPI - NFC chipselect | | 0xF0005104 | 0xFF01 | 0xC300  | DRC SPI - NFC chipselect |
 | 0xF0005108 | 0xFF01 | 0x8000  | "GPIO1" - Flash WP (write protect) | | 0xF0005108 | 0xFF01 | 0x8000  | "GPIO1" - Flash WP (write protect) |
-| 0xF000510C | 0xFF01 | 0xD800  | "GPIO2" - NFC - IRQ out (from NFC module) | +| 0xF000510C | 0xFF01 | 0xD800  | "GPIO2" - NFC - IRQ in (from NFC module) | 
-| 0xF0005110 | 0xFF01 | 0xF200  | "GPIO3" - NFC - IRQ in (to NFC module) |+| 0xF0005110 | 0xFF01 | 0xF200  | "GPIO3" - NFC - IRQ out (to NFC module) |
 | 0xF0005114 | 0xFF01 | 0x8000  | "GPIO4" - Rumble motor | | 0xF0005114 | 0xFF01 | 0x8000  | "GPIO4" - Rumble motor |
 | 0xF0005118 | 0xFF01 | 0x8000  | "GPIO5" - Sensor bar power | | 0xF0005118 | 0xFF01 | 0x8000  | "GPIO5" - Sensor bar power |
Line 83: Line 83:
  
 Note: when the LSB of the hardware ID register (0xF0000000) is 0x41, bits 14 and 15 are swapped. The initial values applied by the stock firmware are also different for some registers, one of them even has bit 16 set? Note: when the LSB of the hardware ID register (0xF0000000) is 0x41, bits 14 and 15 are swapped. The initial values applied by the stock firmware are also different for some registers, one of them even has bit 16 set?
 +
 +There are probably settings for output drive strength. Not sure how to verify/measure that.
  
 Important note: improper GPIO configurations may cause shorts, which will trigger safety shutdown. Important note: improper GPIO configurations may cause shorts, which will trigger safety shutdown.
gpio.1747136144.txt.gz · Last modified: 2025/05/13 11:35 by arisotura

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