WiiU Gamepad Technical Documentation

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gpio [2025/03/20 18:04] – arisoturagpio [2025/05/13 11:38] (current) – arisotura
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 Here is a list of the known GPIO registers, as well as the values the stock firmware initializes them to. Here is a list of the known GPIO registers, as well as the values the stock firmware initializes them to.
 ^ Address    ^ Mask   ^ Init.   ^ Desc. ^ ^ Address    ^ Mask   ^ Init.   ^ Desc. ^
-| 0xF000502C | 0xC000 | 0x8000  | ? | +| 0xF000502C | 0xC000 | 0x8000  | ? (could be LCD pixel clock?) | 
-| 0xF0005038 | 0xC000 | 0x8000  | ? | +| 0xF0005038 | 0xC000 | 0x8000  | Audio related? | 
-| 0xF000503C | 0xCF01 | 0x0001  | Audio - ? | +| 0xF000503C | 0xCF01 | 0x0001  | Audio - sample clock | 
-| 0xF0005040 | 0xCF01 | 0x0001  | Audio - ? | +| 0xF0005040 | 0xCF01 | 0x0001  | Audio - bit clock | 
-| 0xF0005044 | 0xCF01 | 0x0001  | Audio - ? | +| 0xF0005044 | 0xCF01 | 0x0001  | Audio - microphone input | 
-| 0xF0005048 | 0xC000 | 0x8000  | ? | +| 0xF0005048 | 0xC000 | 0x8000  | Audio related? | 
-| 0xF000504C | 0xCF01 | 0x0001  | ? | +| 0xF000504C | 0xCF01 | 0x0001  | Camera - DATA2 | 
-| 0xF0005050 | 0xCF01 | 0x0001  | ? | +| 0xF0005050 | 0xCF01 | 0x0001  | Camera - DATA3 | 
-| 0xF0005054 | 0xCF01 | 0x0001  | ? | +| 0xF0005054 | 0xCF01 | 0x0001  | Camera - DATA4 | 
-| 0xF0005058 | 0xCF01 | 0x0001  | ? | +| 0xF0005058 | 0xCF01 | 0x0001  | Camera - DATA5 | 
-| 0xF000505C | 0xCF01 | 0x0001  | ? | +| 0xF000505C | 0xCF01 | 0x0001  | Camera - DATA6 | 
-| 0xF0005060 | 0xCF01 | 0x0001  | ? | +| 0xF0005060 | 0xCF01 | 0x0001  | Camera - DATA7 | 
-| 0xF0005064 | 0xCF01 | 0x0001  | ? | +| 0xF0005064 | 0xCF01 | 0x0001  | Camera - DATA8 | 
-| 0xF0005068 | 0xCF01 | 0x0001  | ? | +| 0xF0005068 | 0xCF01 | 0x0001  | Camera - DATA9 | 
-| 0xF000506C | 0xCF01 | 0x0001  | ? | +| 0xF000506C | 0xCF01 | 0x0001  | Camera - HREF (HSync output) | 
-| 0xF0005070 | 0xCF01 | 0x0001  | ? | +| 0xF0005070 | 0xCF01 | 0x0001  | Camera - VSYNC (VSync output) | 
-| 0xF0005074 | 0xCF01 | 0x8001  | ? | +| 0xF0005074 | 0xCF01 | 0x8001  | Camera - XVCLK1 (clock input) | 
-| 0xF0005078 | 0xCF01 | 0x0001  | ? |+| 0xF0005078 | 0xCF01 | 0x0001  | Camera - PCLK (pixel clock output) |
 | 0xF0005080 | 0xCF01 | 0x0000  | ? | | 0xF0005080 | 0xCF01 | 0x0000  | ? |
 | 0xF0005084 | 0xCF01 | 0x0000  | ? | | 0xF0005084 | 0xCF01 | 0x0000  | ? |
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 | 0xF0005090 | 0xCF01 | 0x0000  | ? | | 0xF0005090 | 0xCF01 | 0x0000  | ? |
 | 0xF0005094 | 0xCF01 | 0x0000  | ? | | 0xF0005094 | 0xCF01 | 0x0000  | ? |
-| 0xF0005098 | 0xFF01 | 0xC000  | ? |+| 0xF0005098 | 0xFF01 | 0xC000  | "GPIO7" - ? |
 | 0xF000509C | 0xCF01 | 0x8001  | DRC I2C - SCL | | 0xF000509C | 0xCF01 | 0x8001  | DRC I2C - SCL |
 | 0xF00050A0 | 0xCF01 | 0x8001  | DRC I2C - SDA | | 0xF00050A0 | 0xCF01 | 0x8001  | DRC I2C - SDA |
-| 0xF00050AC | 0xFF01 | 0xC001  | SDIO - clock? | +| 0xF00050AC | 0xFF01 | 0xC001  | SDIO - clock | 
-| 0xF00050B0 | 0xFF01 | 0xC001  | SDIO - CMD? |+| 0xF00050B0 | 0xFF01 | 0xC001  | SDIO - CMD |
 | 0xF00050B4 | 0xFF01 | 0xC001  | SDIO - DAT0 | | 0xF00050B4 | 0xFF01 | 0xC001  | SDIO - DAT0 |
 | 0xF00050B8 | 0xFF01 | 0xC001  | SDIO - DAT1/IRQ | | 0xF00050B8 | 0xFF01 | 0xC001  | SDIO - DAT1/IRQ |
-| 0xF00050BC | 0xFF01 | 0xC001  | SDIO - DAT2? | +| 0xF00050BC | 0xFF01 | 0xC001  | SDIO - DAT2 | 
-| 0xF00050C0 | 0xFF01 | 0xC001  | SDIO - DAT3? |+| 0xF00050C0 | 0xFF01 | 0xC001  | SDIO - DAT3 |
 | 0xF00050C4 | 0xCF01 | 0x0000  | ? | | 0xF00050C4 | 0xCF01 | 0x0000  | ? |
 | 0xF00050C8 | 0xCF01 | 0x0000  | ? | | 0xF00050C8 | 0xCF01 | 0x0000  | ? |
 | 0xF00050CC | 0xCF01 | 0x0000  | ? | | 0xF00050CC | 0xCF01 | 0x0000  | ? |
 | 0xF00050D0 | 0xCF01 | 0x0000  | ? | | 0xF00050D0 | 0xCF01 | 0x0000  | ? |
-| 0xF00050D4 | 0xCF01 | 0x8001  | ? | +| 0xF00050D4 | 0xCF01 | 0x8001  | UART1 - TX | 
-| 0xF00050D8 | 0xCF01 | 0x0001  | ? | +| 0xF00050D8 | 0xCF01 | 0x0001  | UART1 - RX | 
-| 0xF00050DC | 0xCF01 | 0x8001  | ? | +| 0xF00050DC | 0xCF01 | 0x8001  | UART2 - IR TX | 
-| 0xF00050E0 | 0xCF01 | 0x8001  | ? | +| 0xF00050E0 | 0xCF01 | 0x8001  | UART2 - IR LED (above transceiver) | 
-| 0xF00050E4 | 0xCF01 | 0x0001  | ? | +| 0xF00050E4 | 0xCF01 | 0x0001  | UART2 - IR RX | 
-| 0xF00050E8 | 0xCF01 | 0x0001  | ? |+| 0xF00050E8 | 0xCF01 | 0x0001  | UART2 - IR PWDOWN |
 | 0xF00050EC | 0xCF01 | 0x8001  | DRC SPI - clock | | 0xF00050EC | 0xCF01 | 0x8001  | DRC SPI - clock |
 | 0xF00050F0 | 0xCF01 | 0x0001  | DRC SPI - MISO | | 0xF00050F0 | 0xCF01 | 0x0001  | DRC SPI - MISO |
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 | 0xF00050F8 | 0xCF01 | 0xC300  | DRC SPI - Flash chipselect | | 0xF00050F8 | 0xCF01 | 0xC300  | DRC SPI - Flash chipselect |
 | 0xF00050FC | 0xCF01 | 0xC300  | DRC SPI - UIC chipselect | | 0xF00050FC | 0xCF01 | 0xC300  | DRC SPI - UIC chipselect |
-| 0xF0005100 | 0xFF01 | 0xC200  | LCD - ?? toggled before I2C comm. | +| 0xF0005100 | 0xFF01 | 0xC200  | "GPIO0" - LCD - ?? toggled before I2C comm. | 
-| 0xF0005104 | 0xFF01 | 0xC300  | DRC SPI - NFC chipselect(?) | +| 0xF0005104 | 0xFF01 | 0xC300  | DRC SPI - NFC chipselect | 
-| 0xF0005108 | 0xFF01 | 0x8000  | ? | +| 0xF0005108 | 0xFF01 | 0x8000  | "GPIO1" - Flash WP (write protect) | 
-| 0xF000510C | 0xFF01 | 0xD800  | ? - NFC related | +| 0xF000510C | 0xFF01 | 0xD800  | "GPIO2" - NFC - IRQ in (from NFC module) | 
-| 0xF0005110 | 0xFF01 | 0xF200  | ? - NFC related | +| 0xF0005110 | 0xFF01 | 0xF200  | "GPIO3" - NFC - IRQ out (to NFC module) | 
-| 0xF0005114 | 0xFF01 | 0x8000  | Rumble motor | +| 0xF0005114 | 0xFF01 | 0x8000  | "GPIO4" - Rumble motor | 
-| 0xF0005118 | 0xFF01 | 0x8000  | Sensor bar power | +| 0xF0005118 | 0xFF01 | 0x8000  | "GPIO5" - Sensor bar power | 
-| 0xF000511C | 0xFF01 | 0x8000  | ? - camera related |+| 0xF000511C | 0xFF01 | 0x8000  | "GPIO6" - Camera RESET |
  
 GPIO register format: GPIO register format:
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 Bit 0 must be set for GPIO ports that are used by other hardware components (ie. SPI, I2C, ...). When bit 0 is set, the output value in bit 8 is ignored, and the input value in bit 10 seems to read as something regardless of bit 11. Bit 0 must be set for GPIO ports that are used by other hardware components (ie. SPI, I2C, ...). When bit 0 is set, the output value in bit 8 is ignored, and the input value in bit 10 seems to read as something regardless of bit 11.
 +
 +An exception to this rule is the ports which lack bit 0 (and bits 8-11): 0xF000502C, 0xF0005038 and 0xF0005048. Those can't be directly controlled.
  
 Setting both bit 9 and bit 11 will cause the output value in bit 8 to be mirrored in bit 10. Setting both bit 9 and bit 11 will cause the output value in bit 8 to be mirrored in bit 10.
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 Note: when the LSB of the hardware ID register (0xF0000000) is 0x41, bits 14 and 15 are swapped. The initial values applied by the stock firmware are also different for some registers, one of them even has bit 16 set? Note: when the LSB of the hardware ID register (0xF0000000) is 0x41, bits 14 and 15 are swapped. The initial values applied by the stock firmware are also different for some registers, one of them even has bit 16 set?
 +
 +There are probably settings for output drive strength. Not sure how to verify/measure that.
  
 Important note: improper GPIO configurations may cause shorts, which will trigger safety shutdown. Important note: improper GPIO configurations may cause shorts, which will trigger safety shutdown.
 +
 +
 +===== Prototype stuff? =====
 +
 +0xF0005108 is used by the bootloader: it is set to 1 when sending certain SPI FLASH commands, and back to 0 when done.
 +
 +It isn't used by the firmware. It is likely a prototype remain -- it probably controlled a status LED on prototype hardware to indicate FLASH access, but the retail gamepad has no such LED.
  
gpio.1742493845.txt.gz · Last modified: 2025/03/20 18:04 by arisotura
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