dma
Differences
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| dma [2025/04/16 12:12] – arisotura | dma [2025/04/20 19:10] (current) – arisotura | ||
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| | 1-3 | Peripheral select | | | 1-3 | Peripheral select | | ||
| - | The peripheral select determines which peripheral is accessed. | + | The peripheral select determines which peripheral is accessed. |
| ^ Value ^ Desc. ^ | ^ Value ^ Desc. ^ | ||
| | 0 | ?? | | | 0 | ?? | | ||
| + | | 1 | ?? | | ||
| | 2 | SPI | | | 2 | SPI | | ||
| | 3 | ?? | | | 3 | ?? | | ||
| - | | 4 | + | | 4 |
| - | | 6 | + | | 5 | UART1 | |
| + | | 6 | ||
| + | | 7 | ?? | | ||
| + | |||
| + | Values 0, 2, 3, 4, 6 occur in the stock firmware. | ||
| Note that the peripheral must be configured correctly for the DMA transfer to work, ie. for SPI, the transfer direction in 0xF0004404 must match that of the DMA channel, and so on. | Note that the peripheral must be configured correctly for the DMA transfer to work, ie. for SPI, the transfer direction in 0xF0004404 must match that of the DMA channel, and so on. | ||
| Line 168: | Line 173: | ||
| | 9 | Bit order for masked fill mode; 0=MSb first, 1=LSb first | | | 9 | Bit order for masked fill mode; 0=MSb first, 1=LSb first | | ||
| | 10 | Simple fill mode (has priority over bit 7) | | | 10 | Simple fill mode (has priority over bit 7) | | ||
| - | | 16-17 | N value for bit 18; 0=1 byte, 1=2 bytes, 2=4 bytes, | + | | 16-17 | N value for bit 18; 0=1 byte, 1=2 bytes, 2=4 bytes, |
| | 18 | Skip every other N source bytes | | | 18 | Skip every other N source bytes | | ||
| | 19 | Apply memory offsets to source address | | | 19 | Apply memory offsets to source address | | ||
dma.1744805547.txt.gz · Last modified: 2025/04/16 12:12 by arisotura