dma
Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| dma [2025/04/16 02:28] – arisotura | dma [2025/04/20 19:10] (current) – arisotura | ||
|---|---|---|---|
| Line 33: | Line 33: | ||
| ^ Bits ^ Desc. ^ | ^ Bits ^ Desc. ^ | ||
| | 0 | DMA enable | | | 0 | DMA enable | | ||
| - | | 2-7 | ?? maybe affects | + | | 2-7 | DMA memory priority? | |
| | 15 | ?? no observed effect | | | 15 | ?? no observed effect | | ||
| + | |||
| + | Bit 0 seems to also control framebuffer transfer to the LCD? When it is cleared, the screen stops refreshing. | ||
| Bit 1 is set by the bootloader, but it doesn' | Bit 1 is set by the bootloader, but it doesn' | ||
| - | Bit 2-7 are set to zero. Not clear what their effect | + | Bit 2-7 are set to zero. They probably affect the priority of DMA relative to the CPU and other devices that access RAM. 0 is the fastest setting for DMA. 63 is the slowest, making |
| Bit 15 is set by the firmware but not the bootloader. | Bit 15 is set by the firmware but not the bootloader. | ||
| Line 77: | Line 79: | ||
| | 1-3 | Peripheral select | | | 1-3 | Peripheral select | | ||
| - | The peripheral select determines which peripheral is accessed. | + | The peripheral select determines which peripheral is accessed. |
| ^ Value ^ Desc. ^ | ^ Value ^ Desc. ^ | ||
| | 0 | ?? | | | 0 | ?? | | ||
| + | | 1 | ?? | | ||
| | 2 | SPI | | | 2 | SPI | | ||
| | 3 | ?? | | | 3 | ?? | | ||
| - | | 4 | + | | 4 |
| - | | 6 | + | | 5 | UART1 | |
| + | | 6 | ||
| + | | 7 | ?? | | ||
| + | |||
| + | Values 0, 2, 3, 4, 6 occur in the stock firmware. | ||
| Note that the peripheral must be configured correctly for the DMA transfer to work, ie. for SPI, the transfer direction in 0xF0004404 must match that of the DMA channel, and so on. | Note that the peripheral must be configured correctly for the DMA transfer to work, ie. for SPI, the transfer direction in 0xF0004404 must match that of the DMA channel, and so on. | ||
| Line 166: | Line 173: | ||
| | 9 | Bit order for masked fill mode; 0=MSb first, 1=LSb first | | | 9 | Bit order for masked fill mode; 0=MSb first, 1=LSb first | | ||
| | 10 | Simple fill mode (has priority over bit 7) | | | 10 | Simple fill mode (has priority over bit 7) | | ||
| - | | 16-17 | N value for bit 18; 0=1 byte, 1=2 bytes, 2=4 bytes, | + | | 16-17 | N value for bit 18; 0=1 byte, 1=2 bytes, 2=4 bytes, |
| - | | 18 | Skip every N other source bytes | | + | | 18 | Skip every other N source bytes | |
| | 19 | Apply memory offsets to source address | | | 19 | Apply memory offsets to source address | | ||
| | 20 | Apply memory offsets to destination address | | | 20 | Apply memory offsets to destination address | | ||
dma.1744770516.txt.gz · Last modified: 2025/04/16 02:28 by arisotura