Differences

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--- dma [2025/04/16 02:14] – arisotura
+++ dma [2025/04/20 19:10] (current) – arisotura
@@ Line 33: / Line 33: @@
 ^ Bits ^ Desc. ^
 | 0    | DMA enable |
-| 2-7  | ?? maybe affects DMA speed? |
+| 2-7  | DMA memory priority? |
 | 15   | ?? no observed effect |
+Bit 0 seems to also control framebuffer transfer to the LCD? When it is cleared, the screen stops refreshing.
 Bit 1 is set by the bootloader, but it doesn't seem to actually exist (or is write-only?).
-Bit 2-7 are set to zero. Not clear what their effect is, maybe they affect DMA speed.
+Bit 2-7 are set to zero. They probably affect the priority of DMA relative to the CPU and other devices that access RAM. 0 is the fastest setting for DMA. 63 is the slowest, making DMA about 9 times slower than 0.
 Bit 15 is set by the firmware but not the bootloader.
@@ Line 77: / Line 79: @@
 | 1-3  | Peripheral select |
-The peripheral select determines which peripheral is accessed. The following values are observed in the stock firmware:
+The peripheral select determines which peripheral is accessed. Here are the known settings:
 ^ Value ^ Desc. ^
 | 0     | ??    |
+| 1     | ??    |
 | 2     | SPI   |
 | 3     | ??    |
-| 4     | ??    |
+| 4     | UART0 |
-| 6     | IR    |
+| 5     | UART1 |
+| 6     | UART2 |
+| 7     | ??    |
+Values 0, 2, 3, 4, 6 occur in the stock firmware.
 Note that the peripheral must be configured correctly for the DMA transfer to work, ie. for SPI, the transfer direction in 0xF0004404 must match that of the DMA channel, and so on.
@@ Line 136: / Line 143: @@
 | 0x20   | Fill value 1 |
 | 0x24   | Fill value 2 |
-| 0x28   | ??? |
+| 0x28   | Positive memory offset |
-| 0x2C   | ??? |
+| 0x2C   | Negative memory offset |
@@ Line 166: / Line 173: @@
 | 9    | Bit order for masked fill mode; 0=MSb first, 1=LSb first |
 | 10   | Simple fill mode (has priority over bit 7) |
-| 16-17 | N value for bit 18; 0=1 byte, 1=2 bytes, 2=4 bytes, 4=8 bytes |
+| 16-17 | N value for bit 18; 0=1 byte, 1=2 bytes, 2=4 bytes, 3=8 bytes |
-| 18   | Skip every N other source bytes |
+| 18   | Skip every other N source bytes |
-| 19   | Read zeroes instead of source data(?) |
+| 19   | Apply memory offsets to source address |
-| 20   | Write back to source (instead of destination) (NOT RIGHT!) |
+| 20   | Apply memory offsets to destination address |
 The logic operator bits specify how the source and destination data are combined. The following operators exist:
@@ Line 200: / Line 207: @@
 When bit 18 is set, twice as much source data is read. This bit also applies in masked fill mode.
+Bits 19 and 20 allow to apply fixed offsets to the source and destination addresses.
@@ Line 269: / Line 278: @@
 **Base+0x28**
+Positive memory offset. When bit 19 of the control register are set, this offset is added to the source address. When bit 20 is set, this offset is added to the destination address.
+Mask is 0x3FFFF0, thus the offset is expressed in 16-byte units.
+Not sure what the intended use of this register is, or if there's a way to have it auto-update under certain circumstances?
 **Base+0x2C**
-Unknown. Mask is 0x003FFFF0. Might be a memory address? (for what?)
+Negative memory offset. Same function as base+0x28, except this offset is subtracted from source/destination addresses.