Differences

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--- dma [2025/04/15 23:01] – arisotura
+++ dma [2025/04/20 19:10] (current) – arisotura
@@ Line 33: / Line 33: @@
 ^ Bits ^ Desc. ^
 | 0    | DMA enable |
-| 2-7  | ?? maybe affects DMA speed? |
+| 2-7  | DMA memory priority? |
 | 15   | ?? no observed effect |
+Bit 0 seems to also control framebuffer transfer to the LCD? When it is cleared, the screen stops refreshing.
 Bit 1 is set by the bootloader, but it doesn't seem to actually exist (or is write-only?).
-Bit 2-7 are set to zero. Not clear what their effect is, maybe they affect DMA speed.
+Bit 2-7 are set to zero. They probably affect the priority of DMA relative to the CPU and other devices that access RAM. 0 is the fastest setting for DMA. 63 is the slowest, making DMA about 9 times slower than 0.
 Bit 15 is set by the firmware but not the bootloader.
@@ Line 77: / Line 79: @@
 | 1-3  | Peripheral select |
-The peripheral select determines which peripheral is accessed. The following values are observed in the stock firmware:
+The peripheral select determines which peripheral is accessed. Here are the known settings:
 ^ Value ^ Desc. ^
 | 0     | ??    |
+| 1     | ??    |
 | 2     | SPI   |
 | 3     | ??    |
-| 4     | ??    |
+| 4     | UART0 |
-| 6     | IR    |
+| 5     | UART1 |
+| 6     | UART2 |
+| 7     | ??    |
+Values 0, 2, 3, 4, 6 occur in the stock firmware.
 Note that the peripheral must be configured correctly for the DMA transfer to work, ie. for SPI, the transfer direction in 0xF0004404 must match that of the DMA channel, and so on.
@@ Line 94: / Line 101: @@
 This register is 12 bits wide.
+Setting this register to zero will treat the memory buffer as a contiguous buffer, ignoring the stride register.
 Setting this register to a value greater than the memory buffer stride will result in DMA malfunction.
@@ Line 134: / Line 143: @@
 | 0x20   | Fill value 1 |
 | 0x24   | Fill value 2 |
+| 0x28   | Positive memory offset |
+| 0x2C   | Negative memory offset |
@@ Line 156: / Line 167: @@
 | 0    | Reverse byte order in each 16-byte block |
 | 1    | Reverse byte order in each 8-byte block |
-| 2-5  | Source address control |
+| 2-5  | Logic operator |
 | 6    | Fill unit; 0=8-bit, 1=16-bit |
 | 7    | Masked fill mode |
@@ Line 162: / Line 173: @@
 | 9    | Bit order for masked fill mode; 0=MSb first, 1=LSb first |
 | 10   | Simple fill mode (has priority over bit 7) |
-| 11   | ??? |
+| 16-17 | N value for bit 18; 0=1 byte, 1=2 bytes, 2=4 bytes, 3=8 bytes |
-| 16   | ??? |
+| 18   | Skip every other N source bytes |
-| 17   | ??? |
+| 19   | Apply memory offsets to source address |
-| 18   | Double source increment every 8 bytes |
+| 20   | Apply memory offsets to destination address |
-| 19   | ??? |
-| 20   | ??? |
-The source address control specifies how the source address is handled during the transfer. Individual bits seem to control individual parts of the address. The useful values are as follows:
+The logic operator bits specify how the source and destination data are combined. The following operators exist:
-^ Value ^ Desc. ^
+^ Value ^ Operator       ^ Desc. ^
-| 0x0   | Fill destination with 0x00 |
+| 0x0   | Clear          | dst = 0x00 |
-| 0x3   | Decrement source address |
+| 0x1   | NOR            | dst = !(dst OR src) |
-| 0xC   | Increment source address |
+| 0x2   | AND inverted   | dst = dst AND !src |
-| 0xF   | Fill destination with 0xFF |
+| 0x3   | Copy inverted  | dst = !src |
+| 0x4   | AND reverse    | dst = !dst AND src |
+| 0x5   | Invert         | dst = !dst |
+| 0x6   | Exclusive OR   | dst = dst XOR src |
+| 0x7   | NAND           | dst = !(dst AND src) |
+| 0x8   | AND            | dst = dst AND src |
+| 0x9   | Equivalence    | dst = !(dst XOR src) |
+| 0xA   | Noop           | dst = dst |
+| 0xB   | OR inverted    | dst = dst OR !src |
+| 0xC   | Copy           | dst = src |
+| 0xD   | OR reverse     | dst = !dst OR src |
+| 0xE   | OR             | dst = dst OR src |
+| 0xF   | Set            | dst = 0xFF |
+Logic operators also apply in fill modes -- in these modes, the source data is the fill color.
 Simple fill mode ignores the source address and fills the destination with fill value 1.
@@ Line 182: / Line 205: @@
 Not yet known if there is a way to do a masked copy.
+When bit 18 is set, twice as much source data is read. This bit also applies in masked fill mode.
+Bits 19 and 20 allow to apply fixed offsets to the source and destination addresses.
@@ Line 189: / Line 216: @@
 This register is 12 bits wide.
+Setting this register to zero will treat the source and destination buffers as contiguous buffers, ignoring the stride registers.
 Setting this register to a value greater than the source or destination buffer stride will result in DMA malfunction.
@@ Line 246: / Line 275: @@
 This register is 16 bits wide.
+**Base+0x28**
+Positive memory offset. When bit 19 of the control register are set, this offset is added to the source address. When bit 20 is set, this offset is added to the destination address.
+Mask is 0x3FFFF0, thus the offset is expressed in 16-byte units.
+Not sure what the intended use of this register is, or if there's a way to have it auto-update under certain circumstances?
+**Base+0x2C**
+Negative memory offset. Same function as base+0x28, except this offset is subtracted from source/destination addresses.