Differences

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--- audio_controller [2025/03/20 17:46] – arisotura
+++ audio_controller [2025/03/21 22:16] (current) – arisotura
@@ Line 1: / Line 1: @@
 ====== Audio controller ======
-The gamepad has a simple audio controller that presumably just streams raw PCM16 to the speakers/headphone jack.
+The audio controller has two main components: output (playing sound to the internal speakers or headphone jack) and input (recording sound from the internal microphone). It supports PCM16 and A-law or µ-law encoded PCM8. Sound output can be mono or stereo, input is always mono.
+Sample frequencies of 48 KHz and 24 KHz are supported. Supporting different frequencies would require reconfiguring the [[audio amplifier]], which is responsible for generating the audio sample/bit clocks.
 Register map:
@@ Line 24: / Line 26: @@
 | 0xF0005440 | counter of sorts? |
 | 0xF0005444 | Input - control register |
-| 0xF0005448 | ??? |
+| 0xF0005448 | Input - count for alert IRQ |
 | 0xF00054A0 | Input - buffer start address |
 | 0xF00054A4 | Input - buffer end address |
-| 0xF00054A8 | Input - current buffer address |
+| 0xF00054A8 | Input - recording end address |
-| 0xF00054B0 | Input - recording count |
+| 0xF00054AC | Input - recording count 1 |
+| 0xF00054B0 | Input - recording count 2 |
 | 0xF00054B4 | Input related?? |
+| 0xF00054B8 | Internal sample counters |
 | 0xF00054C0 | Input - IRQ flags |
 | 0xF00054C4 | Input - IRQ enable |
@@ Line 39: / Line 43: @@
 | 0x17 | Audio output event |
 | 0x18 | Audio input event |
-| 0x1E | Periodic IRQ |
-IRQ 0x17 is used to signal certain events related to audio playback, such as start or end of playback.
-IRQ 0x1E is used by the stock firmware for certain non-audio tasks such as input polling. It seems to always trigger periodically no matter what. I measured the period to be ~5547 microseconds (~600000 cycles), no idea what this represents.
-Not yet known:
-  * if it is possible to play a looping sound (TODO check F0005420 bit0)
-  * how to set the sample rate (prolly directly on the amplifier)
@@ Line 84: / Line 77: @@
 Sound data is transmitted to the amplifier over an I2S interface. The sample clock and bit clock are generated by the amplifier, at speeds of 48 KHz and 3.08 MHz respectively.
-Bits 6-10 control when a sample starts relative to the sample clock edges. The default setting is 1. This setting should match the audio amplifier's data offset setting (page 0 register 28).
+Bits 6-10 control when a sample starts relative to the sample clock edges. The default setting is 1. This setting should match the audio amplifier's data offset setting (page 0 register 28; default setting of 0 means an offset of 1 cycle).
 Bits 11-15 seem to control the bit width of samples. 0 seems to be interpreted as 32. In practice, values 16 and above act the same. The default setting is 0.
@@ Line 122: / Line 115: @@
 Bits 3-27 are writable. It seems that the playback address has a resolution of 16 bytes (atleast with settings: 48KHz stereo 16bit), ie. setting bit 3 will cause the buffer to be played repeatedly.
-Writing to this register while playback is in progress has no effect. TODO: not yet known how to cleanly stop playback.
+Writing to this register while playback is in progress has no effect.
@@ Line 194: / Line 187: @@
 Failure to properly clear these flags will result in IRQs being triggered again and again, effectively freezing the main program.
+**0xF0005440**
+Sample counter of sorts.
+Updated at every sample. During sound output, goes through the following sequence: 00000000, 00000002, 00000004, 00000006, 00000008, 00020008, 00040008, 00060008, 00080008, 0008000A, 0008000C, 0008000E, 00080000, 000A0000, 000C0000, 000E0000.
@@ Line 248: / Line 248: @@
 **0xF00054A8**
-Current recording address.
+Recording end address. This specifies the address at which recording ends.
-TODO how does this work? repeating? etc?
+If this is set to the buffer start address, it is interpreted as the buffer end address.
+This register is not updated by hardware.
-**0xF00054B0**
+Recording always starts at the buffer start address.
+Recording always stops when reaching the end address. Not known if it's possible to do continuous recording.
+**0xF00054AC**
 Recording counter, starts at 0 and increments during recording. Expressed in 16-byte units.
+**0xF00054B0**
+Recording counter, increments during recording. Expressed in 16-byte units.
+Starting value is based on the recording end address in register 0xF00054A8, ie. if 0xF00054A8 is set to 3/4 inside the buffer, this counter starts at 1/4 of the buffer length.
+**0xF00054B8**
+Internal sample counters. They may be used to determine which sample within a given 8-byte chunk is being processed. They are updated once per sample.
+^ Bits  ^ Desc. ^
+| 0-4   | Input L?  |
+| 8-12  | Input R?  |
+| 16-20 | Output L? |
+| 24-28 | Output R? |
+The counters work in a weird way. During sound output, the following sequence is observed: 00000000, 00040000, 00080000, 000C0000, 00100000, 00000000, 04000000, 08000000, 0C000000, 10000000. The input counters follow a similar pattern during recording.
+Maybe the separate counters aren't L/R but more like some double FIFO mechanism for accessing memory?
+Microphone input is monaural, but due to the way the I2S interface works, each sample is repeated twice.
@@ Line 270: / Line 300: @@
 **0xF00054C4**
-Input IRQ enable?
+Input IRQ enable flags.
+Same format as 0xF00054C0. However, a 1 bit //disables// the corresponding IRQ.